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HD66740
HD66740
(112 x 80-dot Graphics LCD Controller/Driver)
Rev 1.0 August, 2001 Description
The HD66740, 112-by-80 dot-matrix graphics LCD controller and driver LSI, displays graphics such as text, kanji and pictograms. It can be configured to drive a dot-matrix liquid crystal under the control of the
microprocessor connected via the clock-synchronized serial or 4/8-bit bus. The HD66740 has a smooth vertical scroll display and a double-height display for the remaining bit map areas. It fixed-displays a part of the graphics icons so that the user can easily see a variety of information. The HD66740 has various functions to reduce the power consumption of an LCD system such as lowvoltage operation of 1.8 V min., a booster to generate maximum five-times LCD drive voltage from the supplied voltage, and voltage-followers to decrease the direct current flow in the LCD drive bleederresistors. Combining these hardware functions with software functions such as standby and sleep modes The HD66740 is suitable for any portable battery-driven product requiring
allows fine power control.
long-term driving capabilities such as cellular phones, pagers, or electronic wallets.
Features
* Control and drive of a graphics LCD * 112 x 80-dot display * Fixed display of graphics icons (pictograms) * Low-power operation support: Vcc = 1.8 to 3.6 V (low voltage) VLCD = 4.5 to 15.0 V (liquid crystal drive voltage) Triple, quadruple, or five-times booster for liquid crystal drive voltage 64-step contrast adjuster and voltage followers to decrease direct current flow in the LCD drive bleeder-resistors Power-save functions such as the standby mode and sleep mode supported Programmable drive duty ratios and bias values displayed on LCD * High-speed clock-synchronized serial interface (serial transfer rate: 5 MHz max.) * I2C bus interface * High-speed 4-/8-bit bus interface capability * 112-segment x 80-common liquid crystal display driver * 1,120-byte (112 x 80 dots) character generator RAM
1
HD66740
* Vertical smooth scroll * Partial smooth scroll control (fixed display of graphics icons) * Vertical double-height display by each display line * Black-and-white reversed display * Wide range of instruction functions: Display on/off control, black-and-white reversed * No wait time for instruction execution and RAM access * Internal oscillation and hardware reset * n-raster-row AC liquid-crystal drive (C-pattern waveform drive) * Shift change of segment and common driver * Tape carrier package (TCP) Table 1 Progammable Display Sizes and Duty Ratios
Graphics Display Duty Ratio 1/32 1/40 1/48 1/56 1/64 1/72 1/80 Optimum Drive Bias 1/7 1/7 1/8 1/8 1/9 1/9.5 1/10 Bit Map 12 x 13-dot Font Width 14 x 15-dot Font Width 2 lines x 8 characters 2.5 lines x 8 characters 3 lines x 8 characters 3.5 lines x 8 characters 4 lines x 8 characters 4.5 lines x 8 characters 5 lines x 8 characters 16 x 16-dot Font Width 2 lines x 7 characters 2.5 lines x 7 characters 3 line x 7 characters 3.5 lines x 7 characters 4 lines x 7 characters 4.5 lines x 7 characters 5 lines x 7 characters
112 x 32 dots 2 lines x 9 characters 112 x 40 dots 3 lines x 9 characters 112 x 48 dots 3 lines x 9 characters 112 x 56 dots 4 lines x 9 characters 112 x 64 dots 5 lines x 9 characters 112 x 72 dots 6 lines x 9 characters 112 x 80 dots 6 lines x 9 characters
2
HD66740
Total Current Consumption Characteristics (Vcc = 3 V, TYP Conditions, LCD Drive Power Current Included)
Total Power Consumption Normal Display Operation Character Display Dot Size Duty Ratio R-C Oscillation Frame Frequency Frequency 75 kHz 75 kHz 75 kHz 75 kHz 75 kHz 80 kHz 90 kHz 73 Hz 73 Hz 74 Hz 74 Hz 73 Hz 70 Hz 70 Hz Internal Logic (27 A) (27 A) (27 A) (27 A) (27 A) (32 A) (35 A) LCD Power (16 A) (16 A) (16 A) (16 A) (18 A) (18 A) (20 A) Sleep Mode Standby Mode
Total* Triple (75 A) Triple (75 A) Triple (75 A) Triple (75 A)
112 x 32 dots 1/32 112 x 40 dots 1/40 112 x 48 dots 1/48 112 x 56 dots 1/56 112 x 64 dots 1/64 112 x 72 dots 1/72 112 x 80 dots 1/80
(15 A) 0.1 A (15 A) (15 A) (15 A)
Quadruple (15 A) (99 A) Quadruple (15 A) (104 A) Five-times (15 A) (135 A)
Note : When a triple, quadruple, or five-times booster is used: the total power consumption = Internal logic current + LCD power current x 3 (triple booster), the total power consumption = Internal logic current + LCD power current x 4 (quadruple booster), and the total power consumption = Internal logic current + LCD power current x 5 (five-times booster)
Type Name
Types HD66740TB0 HD66740WTB0 HCD66740BP HCD66740WBP External Dimensions Bending TCP Bending TCP Au-bumped chip Au-bumped chip Bus Interface 4/8-bits parallel and clock synchronized serial 4/8-bits parallel and I2C bus interface 4/8-bits parallel and clock synchronized serial 4/8-bits parallel and I2C bus interface Operation Voltages 1.8 V to 3.6 V
3
HD66740
LCD Specification Comparison
(Under development) Items Character display sizes Graphic display sizes Multiplexing icons Annunciator Key scan control LED control ports General output ports Operating power voltages Liquid crystal drive voltages I2C bus Serial bus Parallel bus Expansion driver control Liquid crystal drive duty ratios Liquid crystal drive biases Liquid crystal drive waveforms Liquid crystal voltage booster Bleeder-resistor for liquid crystal drive Liquid crystal drive operational amplifier Liquid crystal contrast adjuster Horizontal smooth scroll Vertical smooth scroll Double-height display DDRAM CGROM CGRAM SEGRAM No. of CGROM fonts No. of CGRAM fonts Font sizes Bit map areas R-C oscillation resistor/ oscillation frequency Reset function Low power control HD66725 16 characters x 3 lines 96 x 26 dots 192 1/2 duty: 192 8 x4 -- 3 1.8 V to 5.5 V 3 V to 6 V -- Clock-synchronized serial 4 bits, 8 bits Impossible 1/2, 10, 18, 26 1/4 to 1/6.5 B Single, double, or triple Incorporated (external) Incorporated Incorporated 3-dot unit Line unit Yes 80 x 8 20,736 384 x 8 96 x 8 240 + 192 64 6 x8 96 x 26 External resistor, incorporated (32 kHz) External Partial display off Oscillation off Liquid crystal power off Key wake-up interrupt SEG, COM -- -- TCP-170 -- Yes 170 10.97 x 2.51 80 m HD66728 16 characters x 10 lines 112 x 80 dots -- -- 8 x4 -- 3 1.8 V to 5.5 V 4.5 V to 15 V -- Clock-synchronized serial 4 bits, 8 bits Impossible HD66740 -- 112 x 80 dots -- -- -- -- -- 1.8 V to 3.6 V 4.5 V to 15 V I2C bus interface (HD66740W) Clock-synchronized serial 4 bits, 8 bits Impossible
1/8, 16, 24, 32, 40, 48, 56, 64 1/8, 16, 24, 32, 40, 48, 56, 64 72, 80 72, 80 1/4 to 1/10 B, C Triple, quadruple, or fivetimes Incorporated (external) Incorporated Incorporated -- Line unit Yes 160 x 8 20,736 1,120 x 8 -- 240 + 192 64 6 x8 112 x 80 External resistor (70-90 kHz) External Partial display off Oscillation off Liquid crystal power off Key wake-up interrupt SEG, COM -- -- TCP-243 -- Yes 243 13.67 x 2.78 70 m 1/4 to 1/10 B, C Triple, quadruple, or fivetimes Incorporated (external) Incorporated Incorporated -- Line unit Yes -- -- 1,120 x 8 -- -- -- -- 112 x 80 External resistor (70-90 kHz) External Partial display off Oscillation off Liquid crystal power off SEG, COM -- -- TCP-233 -- Yes 243 9.40 x 2.18 50 m
SEG/COM direction switching QFP package TQFP package TCP package Bare chip Bumped chip No. of pins Chip sizes Pad intervals
4
HD66740
HD66740 Block Diagram
OSC1 OSC2
RESET* TEST
CPG
Timing generator Instruction register (IR) Instruction decoder
8
IM2-1 IM0/ID CS* RS E/WR*/SCL RW/RD*/SDA DB0-DB7
System interface - Clock synchronized serial - I2C bus - 4-bit bus - 8-bit bus
Address counter (AC)
80-bit bidirectional common shift register
Common driver
COM1/80-- COM80/1
8
Data register (DR)
112-bit 112-bit Segment SEG112/1 segment latch driver shift circuit register 8 10
SEG1/112--
Character generator RAM (CGRAM) 1,120 bytes Vci 8 C1+ C1C2+ C2C3+ C3C4+ C4VLOUT Triple to five-times booster
LCD drive voltage selector
Parallel/serial converter
Contrast adjuster Vcc VTEST1-- VTEST3 VR VLCD OPOFF
Drive bias controller
+R
+R
+R0
+R
+-
V1OUT
V2OUT
V3OUT
V4OUT
V5OUT
GND
5
HD66740
HD66740 Pad Arrangement
- Chip size : 9.40mm x 2.18mm - Chip thickness : 550um (typ.) - PAD coordinates : PAD center - Coodinate origin : Chip center - Au bump size (pin number is shown in the blacket) (1)80um x 80um Dummy1(1) to Dummy2(78), Dummy3(104), Dummy20(263) (2)45um x 80um COM34(105) to COM80(119) Dummy4(120) Dummy5(121) to Dummy10(126) Dummy13(241) to Dummy18(246) Dummy19(247) COM72(248) to COM58(262) (3)80um x 45um COM57(264) to COM1(288) COM9(79) to COM33(103) (4)35um x 80um Dummy11(127) SEG1(128) to SEG112(239) Dummy12(240) - Au bump pitch: Refer PAD coodinate - Au bump height : 15um(typ.) - No cross recognition mark
Rev 0.5
Dummy20 COM58/23 COM59/22 COM60/21 COM61/20 COM62/19 COM63/18 COM64/17 COM65/16 COM66/15 COM67/14 COM68/13 COM69/12 COM70/11 COM71/10 COM72/9 Dummy19 Dummy18 Dummy17 Dummy16 Dummy15 Dummy14 Dummy13 Dummy12 SEG112/1 SEG111/2 SEG110/3 SEG109/4 SEG108/5 SEG107/6 SEG106/7 SEG105/8 SEG104/9 SEG103/10 SEG102/11 SEG101/12 SEG100/13 SEG99/14 SEG98/15 SEG97/16 SEG96/17 SEG95/18 SEG94/19 SEG93/20 SEG92/21 SEG91/22 SEG90/23 SEG89/24 SEG88/25 SEG87/26 SEG86/27 SEG85/28 SEG84/29 SEG83/30 SEG82/31 SEG81/32 SEG80/33 SEG79/34 SEG78/35 SEG77/36 SEG76/37 SEG75/38 SEG74/39 SEG73/40 SEG72/41 SEG71/42 SEG70/43 SEG69/44 SEG68/45 SEG67/46 SEG66/47 SEG65/48 SEG64/49 SEG63/50 SEG62/51 SEG61/52 SEG60/53 SEG59/54 SEG58/55 SEG57/56 SEG56/57 SEG55/58 SEG54/59 SEG53/60 SEG52/61 SEG51/62 SEG50/63 SEG49/64 SEG48/65 SEG47/66 SEG46/67 SEG45/68 SEG44/69 SEG43/70 SEG42/71 SEG41/72 SEG40/73 SEG39/74 SEG38/75 SEG37/76 SEG36/77 SEG35/78 SEG34/79 SEG33/80 SEG32/81 SEG31/82 SEG30/83 SEG29/84 SEG28/85 SEG27/86 SEG26/87 SEG25/88 SEG24/89 SEG23/90 SEG22/91 SEG21/92 SEG20/93 SEG19/94 SEG18/95 SEG17/96 SEG16/97 SEG15/98 SEG14/99 SEG13/100 SEG12/101 SEG11/102 SEG10/103 SEG9/104 SEG8/105 SEG7/106 SEG6/107 SEG5/108 SEG4/109 SEG3/110 SEG2/111 SEG1/112 Dummy11 Dummy10 Dummy9 Dummy8 Dummy7 Dummy6 Dummy5 Dummy4 COM80/1 COM79/2 COM78/3 COM77/4 COM76/5 COM75/6 COM74/7 COM73/8 COM40/41 COM39/42 COM38/43 COM37/44 COM36/45 COM35/46 COM34/47 Dummy3
COM57/24 COM56/25 COM55/26 COM54/27 COM53/28 COM52/29 COM51/30 COM50/31 COM49/32 COM48/33 COM47/34 COM46/35 COM45/36 COM44/37 COM43/38 COM42/39 COM41/40 COM8/73 COM7/74 COM6/75 COM5/76 COM4/77 COM3/78 COM2/79 COM1/80
NO.1
Dummy1 GNDDUM IM2 IM1 IM0/ID VccDUM OPOFF TEST DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RESET* CS* RS E/WR*/SCL RW/RD*/SDA GND GND GND GND GND OSC2 OSC1 Vcc Vcc Vcc Vcc Vci Vci Vci Vci C4+ C4+ C4+ C4C4C4C3+ C3+ C3+ C3C3C3C2+ C2+ C2+ C2C2C2C1+ C1+ C1+ C1C1C1VLOUT VLOUT VLOUT VLOUT VLCD VLCD VLCD VLCD V1OUT V2OUT V3OUT V4OUT V5OUT VTEST1 VTEST2 VTEST3 GNDDUM2 Dummy2
NO.264 NO.288 NO.2 NO.263 NO.262
TYPE CODE
HD66740
HD66740
(Top view)
Y
X
NO.77 NO.78 NO.79
NO.105 NO.104 NO.103
COM33/48 COM32/49 COM31/50 COM30/51 COM29/52 COM28/53 COM27/54 COM26/55 COM25/56 COM24/57 COM23/58 COM22/59 COM21/60 COM20/61 COM19/62 COM18/63 COM17/64 COM16/65 COM15/66 COM14/67 COM13/68 COM12/69 COM11/70 COM10/71 COM9/72
6
HD66740
HD66740 Pad Coordinate
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PAD NAME DUMMY1 GNDDUM IM2 IM1 IM0/ID VCCDUM OPOFF TEST DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RESET* CS* RS E/WR*/SCL RW/RD*/SDA GND GND GND GND GND OSC2 OSC1 VCC VCC VCC VCC VCI VCI VCI VCI C4+ C4+ C4+ C4C4C4C3+ C3+ C3+ C3C3C3C2+ C2+ C2+ C2C2C2C1+ C1+ C1+ C1C1C1VLOUT VLOUT VLOUT VLOUT VLCD VLCD VLCD VLCD V1OUT V2OUT V3OUT V4OUT X -4538 -4336 -4190 -4045 -3915 -3813 -3711 -3609 -3466 -3321 -3177 -3032 -2887 -2742 -2597 -2453 -2308 -2163 -2018 -1873 -1729 -1627 -1525 -1423 -1321 -1219 -1117 -972 -791 -689 -587 -485 -332 -230 -128 -26 76 178 280 381 483 585 687 789 891 993 1095 1197 1299 1401 1503 1605 1707 1809 1911 2013 2115 2217 2319 2421 2523 2625 2727 2829 2930 3032 3134 3236 3426 3528 3630 3732 Y -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 -930 No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 PAD NAME V5OUT VTEST1 VTEST2 VTEST3 GNDDUM2 DUMMY2 COM9/72 COM10/71 COM11/70 COM12/69 COM13/68 COM14/67 COM15/66 COM16/65 COM17/64 COM18/63 COM19/62 COM20/61 COM21/60 COM22/59 COM23/58 COM24/57 COM25/56 COM26/55 COM27/54 COM28/53 COM29/52 COM30/51 COM31/50 COM32/49 COM33/48 DUMMY3 COM34/47 COM35/46 COM36/45 COM37/44 COM38/43 COM39/42 COM40/41 COM73/8 COM74/7 COM75/6 COM76/5 COM77/4 COM78/3 COM79/2 COM80/1 DUMMY4 DUMMY5 DUMMY6 DUMMY7 DUMMY8 DUMMY9 DUMMY10 DUMMY11 SEG1/112 SEG2/111 SEG3/110 SEG4/109 SEG5/108 SEG6/107 SEG7/106 SEG8/105 SEG9/104 SEG10/103 SEG11/102 SEG12/101 SEG13/100 SEG14/99 SEG15/98 SEG16/97 SEG17/96 X 3834 3936 4038 4140 4336 4538 4538 4538 4538 4538 4538 4538 4538 4538 4538 4538 4538 4538 4538 4538 4538 4538 4538 4538 4538 4538 4538 4538 4538 4538 4538 4538 4336 4276 4216 4156 4096 4036 3976 3916 3856 3795 3735 3675 3615 3555 3495 3431 3281 3221 3161 3101 3041 2981 2836 2782 2732 2682 2631 2581 2531 2481 2431 2381 2331 2281 2230 2180 2130 2080 2030 1980 Y -930 -930 -930 -930 -930 -930 -721 -661 -601 -541 -481 -421 -361 -301 -240 -180 -120 -60 0 60 120 180 240 301 361 421 481 541 601 661 721 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 No. 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 PAD NAME SEG18/95 SEG19/94 SEG20/93 SEG21/92 SEG22/91 SEG23/90 SEG24/89 SEG25/88 SEG26/87 SEG27/86 SEG28/85 SEG29/84 SEG30/83 SEG31/82 SEG32/81 SEG33/80 SEG34/79 SEG35/78 SEG36/77 SEG37/76 SEG38/75 SEG39/74 SEG40/73 SEG41/72 SEG42/71 SEG43/70 SEG44/69 SEG45/68 SEG46/67 SEG47/66 SEG48/65 SEG49/64 SEG50/63 SEG51/62 SEG52/61 SEG53/60 SEG54/59 SEG55/58 SEG56/57 SEG57/56 SEG58/55 SEG59/54 SEG60/53 SEG61/52 SEG62/51 SEG63/50 SEG64/49 SEG65/48 SEG66/47 SEG67/46 SEG68/45 SEG69/44 SEG70/43 SEG71/42 SEG72/41 SEG73/40 SEG74/39 SEG75/38 SEG76/37 SEG77/36 SEG78/35 SEG79/34 SEG80/33 SEG81/32 SEG82/31 SEG83/30 SEG84/29 SEG85/28 SEG86/27 SEG87/26 SEG88/25 SEG89/24 X 1930 1880 1829 1779 1729 1679 1629 1579 1529 1479 1428 1378 1328 1278 1228 1178 1128 1078 1028 977 927 877 827 777 727 677 627 576 526 476 426 376 326 276 226 175 125 75 25 -25 -75 -125 -175 -226 -276 -326 -376 -426 -476 -526 -576 -627 -677 -727 -777 -827 -877 -927 -977 -1028 -1078 -1128 -1178 -1228 -1278 -1328 -1378 -1428 -1479 -1529 -1579 -1629 Y 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 No. 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288
2000.06.13 (Unit : um)
PAD NAME SEG90/23 SEG91/22 SEG92/21 SEG93/20 SEG94/19 SEG95/18 SEG96/17 SEG97/16 SEG98/15 SEG99/14 SEG100/13 SEG101/12 SEG102/11 SEG103/10 SEG104/9 SEG105/8 SEG106/7 SEG107/6 SEG108/5 SEG109/4 SEG110/3 SEG111/2 SEG112/1 DUMMY12 DUMMY13 DUMMY14 DUMMY15 DUMMY16 DUMMY17 DUMMY18 DUMMY19 COM72/9 COM71/10 COM70/11 COM69/12 COM68/13 COM67/14 COM66/15 COM65/16 COM64/17 COM63/18 COM62/19 COM61/20 COM60/21 COM59/22 COM58/23 DUMMY20 COM57/24 COM56/25 COM55/26 COM54/27 COM53/28 COM52/29 COM51/30 COM50/31 COM49/32 COM48/33 COM47/34 COM46/35 COM45/36 COM44/37 COM43/38 COM42/39 COM41/40 COM8/73 COM7/74 COM6/75 COM5/76 COM4/77 COM3/78 COM2/79 COM1/80 X -1679 -1729 -1779 -1829 -1880 -1930 -1980 -2030 -2080 -2130 -2180 -2230 -2281 -2331 -2381 -2431 -2481 -2531 -2581 -2631 -2682 -2732 -2782 -2836 -2981 -3041 -3101 -3161 -3221 -3281 -3431 -3495 -3555 -3615 -3675 -3735 -3795 -3856 -3916 -3976 -4036 -4096 -4156 -4216 -4276 -4336 -4538 -4538 -4538 -4538 -4538 -4538 -4538 -4538 -4538 -4538 -4538 -4538 -4538 -4538 -4538 -4538 -4538 -4538 -4538 -4538 -4538 -4538 -4538 -4538 -4538 -4538 Y 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 928 721 661 601 541 481 421 361 301 240 180 120 60 0 -60 -120 -180 -240 -301 -361 -421 -481 -541 -601 -661 -721
7
HD66740
TCP Dimensions (HD66740TB0)
Bending slit 4.0 mm
Dummy COM1/80 COM8/73 COM41/40
HD66740
I/O, Power supply 0.65P x (49 - 1) = 31.20 mm
IM2 IM1 IM0/ID OPOFF TEST NC NC NC NC NC NC NC NC DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RESET* CS* RS E/WR*/SCL RW/RD*/SDA GND OSC2 OSC1 Vcc Vci C4+ C4C3+ C3C2+ C2C1+ C1VLOUT VLCD V1OUT V2OUT V3OUT V4OUT V5OUT VTEST1 VTSET2 VTEST3
0.17P x (41 - 1) = 6.80 mm 0.50 mm
0.65-mm pitch
COM72/9 SEG112/1 SEG111/2 SEG110/3 SEG109/4
0.16-mm pitch 32.36 mm LCD drive 0.16P x (112 - 1) = 17.76 mm
SEG4/109 SEG3/110 SEG2/111 SEG1/112 COM80/1 COM73/8 COM40/41
0.50 mm 0.17P x (41 - 1) = 6.80 mm
HITACHI
COM9/72 Dummy
8
HD66740
Pin Functions
Table 2
Signals IM2, IM1
Pin Functional Description
Number of Pins 2 I/O I Connected to GND or VCC Functions Selects the MPU interface mode:
IM2 "GND" "GND" "Vcc" "Vcc" IM1 "GND" "Vcc" "GND" "Vcc" MPU interface mode Clock synchronized serial interface 68-system parallel interface I2C bus interface 80-system parallel interface
IM0/ID
1
I
GND or VCC
Selects the transfer bus length for a parallel bus interface. GND: 8-bit bus, Vcc: 4-bit bus Inputs the ID of the device ID code for a serial bus and I2C bus interface. Selects the HD66740: Low: HD66740 is selected and can be accessed High: HD66740 is not selected and cannot be accessed Must be fixed at GND level when not in use. Selects the register for a parallel bus interface. Low: Instruction High: RAM access Must be fixed at GND level when not in use.
CS*
1
I
MPU
RS
1
I
MPU
E/WR*/SCL
1
I
MPU
For an 80-system parallel bus interface, serves as a write strobe signal and writes data at the low level. For a 68-system parallel bus interface, serves as an enable signal to activate data read/write operation. Inputs the serial transfer clock for a serial interface. Fetches data at the rising edge of a clock. For an 80-system parallel bus interface, serves as a write strobe signal and reads data at the low level. For a 68-system parallel bus interface, serves as a signal to select data read/write operation. Low: Write High: Read Serves as the bidirectional serial transfer data for a serial interface. Sends/Receives data.
RW/RD*/ SDA
1
I or I/O
MPU
9
HD66740
Table 2
Signals DB0-DB7
Pin Functional Description (cont)
Number of Pins I/O 8 Connected to Functions Serves as a bidirectional data bus for a parallel bus interface. For a 4-bit bus, data transfer uses DB7-DB4 Must be fixed at GND level when serial interface mode is used.
I/O or MPU I
COM1/80- 80 COM80/1
O
LCD
Common output signals for graphics display: COM1 to COM8 for the first line, COM9 to COM16 for the second line, COM17 to COM24 for the third line, COM25 to COM32 for the fourth line, and COM73 to COM80 for the 10th line. All the unused pins output unselected waveforms. In the sleep mode (SLP = 1) or standby mode (STB = 1), all pins output GND level. The CMS bit can change the shift direction of the common signal. For example, if CMS = 0, COM1/80 is COM1. If CMS = 1, COM1/80 is COM80. Note that the start position of the common output (the first line) is shifted by CN1-CN0 bits. Segment output signals for graphics display. In the sleep mode (SLP = 1) or standby mode (STB = 1), all pins output GND level. The SGS bit can change the shift direction of the segment signal. For example, if SGS = 0, SEG1/112 is SEG1. If SGS = 1, SEG1/112 is SEG112.
SEG1/112- 112 SEG112/1
O
LCD
V1OUT-V5 5 OUT
I or O Open or Used for output from the internal operational amplifiers external when they are used (OPOFF = GND); attach a bleeder-resistor capacitor to stabilize the output. When the amplifiers are not used (OPOFF = VCC), V1 to V5 voltages can be supplied to these pins externally. -- -- Power supply Power supply Power supply for LCD drive. VLCD - GND = 15 V max. VCC: +1.8 V to +3.6 V; GND (logic): 0 V
VLCD VCC, GND OSC1, OSC2 Vci
3 12 2
I or O OscillationFor R-C oscillation using an external resistor, connect resistor or clock an external resistor. For external clock supply, input clock pulses to OSC1. I Power supply Inputs a reference voltage and supplies power to the booster; generates the liquid crystal display drive voltage from the operating voltage. The boosting output voltage must not be larger than the absolute maximum ratings. Must be left disconnected when the booster is not used.
5
VLOUT
3
O
VLCD pin/booster Potential difference between Vci and GND is triple- to capacitance five-times-boosted and then output. Magnitude of boost is selected by instruction.
10
HD66740
Table 2
Signals C1+, C1- C2+, C2- C3+, C3- C4+, C4- RESET* OPOFF
Pin Functional Description (cont)
Number of Pins I/O 8 6 6 6 1 1 -- -- -- -- I I Connected to Booster capacitance Booster capacitance Booster capacitance Booster capacitance Functions External capacitance should be connected here for boosting. External capacitance should be connected here when using the triple or more booster. External capacitance should be connected here when using the quadruple and five-times booster. External capacitance should be connected here when using the five-times booster.
MPU or external Reset pin. Initializes the LSI when low. R-C circuit VCC or GND Turns the internal operational amplifier off when OPOFF = VCC, and turns it on when OPOFF = GND. If the amplifier is turned off (OPOFF = VCC), V1 to V5 must be supplied to the V1OUT to V5OUT pins. Outputs the internal VCC level; shorting this pin sets the adjacent input pin to the VCC level. Outputs the internal GND level; shorting this pin sets the adjacent input pin to the GND level. Dummy pad. Test pin. Must be left disconnected.
VccDUM GNDDUM Dummy TEST VTEST1
1 1 5 1 1
O O -- I I
Input pins Input pins -- GND GND or VCC
Must be fixed at GND level.
Adjusts the driving capability of the internal operationa amplifier for the LCD. This signal enters the normal drive mode in the GND side, and it enters the highpower drive mode in the VCC side. When the display quality is not sufficient, use the high-power drive mode even though the power-consumption current is large. Test pin. Must be left disconnected.
VTEST2 VTEST3
1 1
-- I
-- VCC or GND
Adjusts the driving capability of the internal operationa amplifier for the LCD. This signal enters the normal drive mode or high-power mode in the GND side according to the VTEST1 pin setting, and it enters the low-power drive mode in the VCC side. Use this signa in the low-power mode so that the display quality is no lowered.
11
HD66740
Block Function Description
System Interface The HD66740 has six types of system interfaces, and a clock-synchronized serial, an I2C bus interface, a 68-system 4-bit/8-bit bus, and a 80-system 4-bit/8-bit bus. The interface mode is selected by the IM2-0 pins. The HD66740 has two 8-bit registers: an instruction register (IR) and a data register (DR). The IR stores instruction codes, such as clear display, display control, and address information for the display character generator RAM (CGRAM). The DR temporarily stores data to be written into the CGRAM. Data written into the DR from the MPU is automatically written into the CGRAM by internal operation. When address information is written into the IR, data is read and then stored in the DR from the CGRAM by internal operation. Data is read through the DR when reading from the RAM, and the first read data is invalid and the second and the following data are normal. After reading, data in the CGRAM at the next address is sent to the DR for the next reading from the MPU. Execution time for instruction excluding clear display is 0 clock cycle and instructions can be written in succession. Table 3
R/W Bit 0 1 0 1
Register Selection by RS and R/W Bits
RS Bit 0 0 1 1 Operations Write instructions to IR DR write as an internal operation (DR to CGRAM) DR read as an internal operation (CGRAM to DR)
Address Counter (AC) The address counter (AC) assigns addresses to the CGRAM. When an address set instruction is written into the IR, the address information is sent from the IR to the AC. After writing into the CGRAM, the AC is automatically incremented by 1 (or decremented by 1). After reading from the data, the RDM bit automatically updates or does not update the AC. Character Generator RAM (CGRAM) The CGRAM serves as a RAM to store 112 x 80-dot bit pattern data in the graphics display mode. display patterns are directly written into CGRAM. For details, see the Graphics Display section. Timing Generator The timing generator generates timing signals for the operation of internal circuits such as the CGRAM. The RAM read timing for display and internal operation timing by MPU access are generated separately to avoid interference with one another. This prevents flickering in areas other than the display area when writing data to the CGRAM, for example. Here,
12
HD66740
Oscillation Circuit (OSC) The HD66740 can provide R-C oscillation simply through the addition of an external oscillation-resistor between the OSC1 and OSC2 pins. The appropriate oscillation frequency for operating voltage, display size, and frame frequency can be obtained by adjusting the external-resistor value. Clock pulses can also be supplied externally. Since R-C oscillation stops during the standby mode, current consumption can be reduced. For details, see the Oscillation circuit section. Liquid Crystal Display Driver Circuit The liquid crystal display driver circuit consists of 80 common signal drivers (COM1 to COM80) and 112 segment signal drivers (SEG1 to SEG112). When the number of lines are selected by a program, the required common signal drivers automatically output drive waveforms, while the other common signal drivers continue to output unselected waveforms. Graphics data is sent serially through a 112-bit shift register and latched when all needed data has arrived. The latched data then enables the segment signal drivers to generate drive waveform outputs. The shift direction of 112-bit data can be changed by the SGS bit. The shift direction for the common driver can also be changed by the CMS bit by selecting an appropriate direction for the device mounting configuration. When display is off, or during the standby or sleep mode, all the above common and segment signal drivers output the GND level, halting the display. Booster (DC-DC Converter) The booster generates triple, quadruple, or five-times voltage input to the Vci pin. With this, both the internal logic units and LCD drivers can be controlled with a single power supply. Boost output level from triple to five-times boost can be selected by software. For details, see the Power Supply for Liquid Crystal Display Drive section. V-Pin Voltage Follower A voltage follower for each voltage level (V1 to V5) reduces current consumption by the LCD drive power supply circuit. No external resistors are required because of the internal bleeder-resistor, which generates different levels of LCD drive voltage. This internal bleeder-resistor can be software-specified from 1/4 bias to 1/10 bias, according to the liquid crystal display drive duty value. The voltage followers can be turned off while multiplexing drive is not being used. For details, see the Power Supply for Liquid Crystal Display Drive section. Contrast Adjuster The contrast adjuster can be used to adjust LCD contrast in 64 steps by varying the LCD drive voltage by software. This can be used to select an appropriate LCD brightness or to compensate for temperature.
13
HD66740
CGRAM Address Map
Table 4
Segment Driver
Relationship between Display Position and CGRAM Address (1)
SEG10/103 SEG11/102 SEG12/101 SEG13/100 SEG1/112 SEG2/111 SEG3/110 SEG4/109 SEG5/108 SEG6/107 SEG7/106 SEG8/105 SEG9/104 SEG14/99 SEG15/98 SEG16/97 SEG17/96 SEG108/5 SEG109/4 SEG110/3 SEG111/2 SEG112/1
0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 Segment
Common
(HEX)
Address
SGS="0" 000 001 002 003 004 005 006 007 008 009 00A 00B 00C 00D 00E 00F 010 SGS="1" 06F 06E 06D 06C 06B 06A 069 068 067 066 065 064 063 062 061 060 05F DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 1 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 1 0 0 1 0 1 1 1 1 1 1 1 1 0 1 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 1 1 1 1 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
06B 06C 06D 06E 06F 004 003 002 001 000 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8
(HEX)
Address
SGS="0" 080 081 082 083 084 085 086 087 088 089 08A 08B 08C 08D 08E 08F 090 SGS="1" 0EF 0EE 0ED0EC0EB 0EA 0E9 0E8 0E7 0E6 0E5 0E4 0E3 0E2 0E1 0E0 0DF DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 1 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
0EB 0EC 0ED 0EE 0EF 084 083 082 081 080 0 1 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0
COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16
(HEX)
Address
SGS="0" 100 101 102 103 104 105 106 107 108 109 10A 10B 10C 10D10E 10F 110 SGS="1" 16F 16E 16D16C 16B 16A 169 168 167 166 165 164 163 162 161 160 15F DB0 DB1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0
16B 16C 16D 16E 16F 104 103 102 101 100 1 0 1 0 1 0 1 1
COM17 COM18
DB7
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
COM24
(HEX)
Address
SGS="0" 180 181 182 183 184 185 186 187 188 189 18A 18B 18C 18D 18E 18F 180 SGS="1" 1EF 1EE 1ED1EC1EB 1EA 1E9 1E8 1E7 1E6 1E5 1E4 1E3 1E2 1E1 1E0 1DF DB0 DB1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
1EB1EC 1ED 1EE 1EF 184 183 182 181 180 0 0 0 0 0 1 1 1 COM25 COM26
DB7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
COM32
(HEX)
Address
SGS="0" 200 201 202 203 204 205 206 207 208 209 20A 20B 20C 20D 20E 20F 210 SGS="1" 26F 26E 26D 26C 26B 26A 269 268 267 266 265 264 263 262 261 260 25F DB0 DB1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
26B 26C 26D 26E 26F 204 203 202 201 200 0 0 0 0 0 1 1 1
COM33 COM34
DB7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
COM40
Notes: 1.
A set bit in CGRAM data 1 corresponds to display selection (lit) and 0 to non-selection (unlit).
14
HD66740
Table 5
Segment Driver
Relationship between Display Position and CGRAM Address (2)
SEG11/102 SEG10/103 SEG12/101 SEG13/100 SEG1/112 SEG2/111 SEG3/110 SEG4/109 SEG5/108 SEG6/107 SEG7/106 SEG8/105 SEG9/104 SEG14/99 SEG15/98 SEG16/97 SEG17/96 SEG108/5 SEG109/4 SEG110/3 SEG111/2 SEG112/1
1 0 0 0 1 1 0 0 1 0 0 1 1 1 0 0 0 0 0 0 1 0 0 1 0 Segment
Common
(HEX)
Address
SGS="0" 280 281 282 283 284 285 286 287 288 289 28A 28B 28C 28D 28E 28F 290 SGS="1" 2EF 2EE 2ED2EC2EB 2EA 2E9 2E8 2E7 2E6 2E5 2E4 2E3 2E2 2E1 2E0 2DF DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 0 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 1 0 0 1 1 1 1 1 1 0 1 1 1 0 1 1 1 0 0 1 0 0 0 1 1 0 1 1 1 0 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 1 0
2EB 2EC 2ED 2EE 2EF 284 283 282 281 280 1 0 0 0 0 1 0 0 1 0 1 0 0 0 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 0
COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48
(HEX)
Address
SGS="0" 300 301 302 303 304 305 306 307 308 309 30A 30B 30C 30D 30E 30F 310 SGS="1" 36F 36E 36D 36C 36B 36A 369 368 367 366 365 364 363 362 361 360 35F DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 1 0 0 1 1 1 1 1 1 0 1 1 1 0 1 1 1 0 0 1 0 0 0 1 1 0 1 1 1 0 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 1 0
36B 36C 36D 36E 36F 304 303 302 301 300 1 1 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 0 1 0 0 0 1 0 1 0 1 0 0 0 1 0 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56
(HEX)
Address
SGS="0" 380 381 382 383 384 385 386 387 388 389 38A 38B 38C 38D 38E 38F 390 SGS="1" 3EF 3EE 3ED3EC 3EB 3EA 3E9 3E8 3E7 3E6 3E5 3E4 3E3 3E2 3E1 3E0 3DF DB0 DB1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1
3EB 3EC 3ED 3EE 3EF 384 383 382 381 380 0 0 0 1 1 1 0 0 COM57 COM58
DB7
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
0
COM64
(HEX)
Address
SGS="0" 400 401 402 403 404 405 406 407 408 409 40A 40B 40C 40D 40E 40F 410 SGS="1" 46F 46E 46D 46C 46B 46A 469 468 467 466 465 464 463 462 461 460 45F DB0 DB1 0 1 1 1 1 1 0 1 0 0 0 1 1 1 1 1 0 1 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1
46B 46C 46D 46E 46F 404 403 402 401 400 0 1 1 0 1 0 1 0 COM65 COM66
DB7
0
0
0
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
COM72
(HEX)
Address
SGS="0" 480 481 482 483 484 485 486 487 488 489 48A 48B 48C 48D 48E 48F 490 SGS="1" 4EF 4EE 4ED4EC4EB 4EA 4E9 4E8 4E7 4E6 4E5 4E4 4E3 4E2 4E1 4E0 4DF DB0 DB1 0 1 1 1 1 1 0 1 0 0 0 1 1 1 1 1 0 1 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1
4EB 4EC 4ED 4EE 4EF 484 483 482 481 480 0 1 1 0 1 0 1 0
COM73 COM74
DB7
0
0
0
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
COM80
Notes: 1.
A set bit in CGRAM data 1 corresponds to display selection (lit) and 0 to non-selection (unlit).
15
HD66740
Instructions
Outline Only the instruction register (IR) and the data register (DR) of the HD66740 can be controlled by the MPU. Before starting internal operation of the HD66740, control information is temporarily stored in these registers to allow interfacing with various peripheral control devices or MPUs which operate at different speeds. The internal operation of the HD66740 is determined by signals sent from the MPU. These signals, which include the register selection signal (RS), the read/write signal (R/W), and the data bus signal (DB0 to DB7), make up the HD66740 instructions. There are four categories of instructions that: * * * * Control the display Control power management Set internal RAM addresses Transfer data with the internal RAM
Normally, instructions that perform data transfer with the internal RAM are used the most. However, auto-incrementation by 1 (or auto-decrementation by 1) of internal HD66740 RAM addresses after each data write can lighten the MPU program load. Because instructions are executed in 0 cycle, instructions can be written in succession.
16
HD66740
Instruction Descriptions
Start Oscillation The start oscillation instruction restarts the oscillator from the halt state in the standby mode. After issuing this instruction, wait at least 10 ms for oscillation to stabilize before issuing the next instruction. (See the Standby Mode section.)
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 1 1
Figure 1 Driver Output Control
Start Oscillation Instruction
CMS: Selects the output shift direction of a common driver. When CMS = "0", COM1/80 shifts to COM1, and COM80/1 to COM80. When CMS = "1", COM1/80 shifts to COM80, and COM80/1 to COM1. Output position of a common driver shifts depending on the CN1-0 bit setting. For details, see the Display On/Off Control section. SGS: Selects the output shift direction of a segment driver. When SGS = "0", SEG1/112 shifts to SEG1, and SEG112/1 to SEG112. When SGS = "1", SEG1/112 shifts SEG112, and SEG112/1 to SEG1.
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 CMS SGS
Figure 2
Driver Output Control Instruction
17
HD66740
Power Control AMP: When AMP = 1, each voltage follower for V1 to V5 pins and the booster are turned on. AMP = 0, current consumption can be reduced while the display is not being used. When
SLP: When SLP = 1, the HD66740 enters the sleep mode, where the internal operations are halted except for the R-C oscillator, thus reducing current consumption. For details, see the Sleep Mode section. Only the power control (AMP, SLP, and STB bits) instruction can be executed during the sleep mode. During the sleep mode, the other RAM data and instructions cannot be updated although they are retained. STB: When STB = 1, the HD66740 enters the standby mode, where display operation completely stops, halting all the internal operations including the internal R-C oscillator. Further, no external clock pulses are supplied. For details, see the Standby Mode section. Only the following instructions can be executed during the standby mode. a. Standby mode cancel (STB = 0) b. Voltage follower circuit on/off (AMP = 1/0) c. Start oscillation During the standby mode, the other RAM data and instructions may be lost. To prevent this, they must be set again after the standby mode is canceled.
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 AMP SLP STB
Figure 3
Power Control Instruction
18
HD66740
Contrast Control 1/2 SW: Switches the bit configuration for the contrast control instruction. CT4-CT0: When SW = 0, they control the LCD drive voltage (potential difference between V1 and GND) to adjust contrast. A 64-step adjustment is also possible by using the CT5 bit which are set in the entry mode register. For details, see the Contrast Adjuster section.
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 0 SW CT4 CT3 (SW = 0) BT1 BT0 (SW = 1)
0
0
0
0
0
1
1
CT2 CT1 CT0 (SW = 0) BS2 BS1 BS0 (SW = 1)
Figure 4
Contrast-Control 1/2 Instruction
VLCD VR R R R0 R R GND
HD66740
+ + + -
V1 V2 V3
+ + -
V4 V5 GND
Figure 5
Contrast Adjuster
19
HD66740
Table 6 CT Bits and Variable Resistor Value of Contrast Adjuster
CT Set Value CT5 0 0 0 0 0 CT4 0 0 0 0 0 CT3 0 0 0 0 0 CT2 0 0 0 0 1 * * 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 * * 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 0 0 1 1 0 1 0 CT1 0 0 1 1 0 CT0 0 1 0 1 0 Variable Resistor (VR) 3.20 x R 3.15 x R 3.10 x R 3.05 x R 3.00 x R * * 1.65 x R 1.60 x R 1.55 x R 1.50 x R * * 0.15 x R 0.10 x R 0.05 x R
BT1-0: When SW = 1, they switch the output of V5OUT between triple, quadruple, and five-times boost. The liquid crystal display drive voltage level can be selected according to its drive duty ratio and bias. A lower amplification of the booster consumes less current. BS2-0: When SW = 1, they set the crystal display drive bias value within the range of 1/4 to 1/10 bias. The liquid crystal display drive bias value can be selected according to its drive duty ratio and voltage. For details, see the Liquid Crystal Display Drive Bias Selector section. Table 7
BT1 0 0 1 1
BT Bits and Output Level
BT0 0 1 0 1 V5OUT Output Level Triple boost Quadruple boost Five-times boost Setting inhibited
20
HD66740
Table 8
BS2 0 0 0 0 1 1 1 1
BS Bits and LCD Drive Bias Value
BS1 0 0 1 1 0 0 1 1 BS0 0 1 0 1 0 1 0 1 Liquid Crystal Display Drive Bias Value 1/10 bias drive 1/9.5 bias drive 1/9 bias drive 1/8 bias drive 1/7 bias drive 1/6 bias drive 1/5 bias drive 1/4 bias drive
21
HD66740
Entry Mode REV: Displays all graphics display sections with black-and-white reversal when SW = 0 and REV = 1. For details, see the Reversed Display Function section. I/D: When SW = 0, increments (I/D = 1) or decrements (I/D = 0) the CGRAM address by 1 when a data is written into or read from the CGRAM. CT5: Sets the most significant bit (CT5) for contrast adjustment when SW = 1. A 64-step adjustment is also possible by using the CT4-CT0 bits which are set in the contrast-control 1/2 instruction. RDM: When SW = 1 and RDM = 0, the RDM increments or decrements the address counter value according to the I/D bit setting after reading the data from the CGRAM. When RDM = 1, the address counter value is not updated after the data has been read from the CGRAM. The address counter value is used when the RAM data is read, modified, and written. Since the first read data is invalid, the read must be continuously done twice. After writing to the RAM, the address counter value must be updated.
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 0 REV I/D CT5 RDM 1 0 (SW = 0) (SW = 1)
Figure 6
Entry Mode Set Instruction
22
HD66740
Display On/Off Control D: Display is on when SW = 0 and D = 1 and off when D = 0. When off, the display data remains in the DDRAM or CGRAM, and can be displayed instantly by setting D = 1. When D is 0, the display is off with the SEG1 to SEG112 outputs and COM1 to COM80 outputs set to the GND level. Because of this, the HD66740 can control charging current for the LCD with AC driving. DL10: When SW = 0, DL10 can be set. When DL10 = 1, the 10th line is displayed at double height.
DL9-DL7: When SW = 1, DL9-DL7 can be set. Double-height display is specified for any display line. When DL7 = 1, the seventh line is displayed at double height. Double-height display is used for the eighth line when DL8 = 1 and for the ninth line when DL9 = 1. For double-height display for the first to the sixth lines, control them by using DL1-DL6 bits in the display-line control instruction.
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 0 D DL10 0 (SW = 0) DL9 DL8 DL7 (SW = 1)
Figure 7
Display On/Off Control Instruction
23
HD66740
Display Line Control NL3-0: Set NL2-NL0 bits when SW = 0, and the NL3 bit when SW = 1 to specify the display lines. Display lines change the liquid crystal display drive duty ratio. CGRAM address mapping does not depend on the number of display lines.
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 1 NL2 NL1 NL0 (SW = 0) CN1 CN0 NL3 (SW = 1)
Figure 8 Table 9
NL3 0 0 0 0 0 0 0 0 1 1 NL2 0 0 0 0 1 1 1 1 0 0
Display-line Control Instruction
NL Bits and Display Lines
NL1 0 0 1 1 0 0 1 1 0 0 NL0 0 1 0 1 0 1 0 1 0 1 Graphics Display 112 x 8 dots 112 x 16 dots 112 x 24 dots 112 x 32 dots 112 x 40 dots 112 x 48 dots 112 x 56 dots 112 x 64 dots 112 x 72 dots 112 x 80 dots LCD Drive Duty 1/8 Duty 1/16 Duty 1/24 Duty 1/32 Duty 1/40 Duty 1/48 Duty 1/56 Duty 1/64 Duty 1/72 Duty 1/80 Duty Common Driver Used COM1-COM8 COM1-COM16 COM1-COM24 COM1-COM32 COM1-COM40 COM1-COM48 COM1-COM56 COM1-COM64 COM1-COM72 COM1-COM80
CN1-CN0: Set CN1-CN0 bits when SW = 1. When CN1-0 = 01, the display position is shifted by 16 dots below and display starts from COM17. When the liquid crystal is driven at low duty in the system wait state, it can display partially at the center of the screen. For details, see the Partial-display-on Function section. When CN1-CN0 = 10, the display position is shifted by 8 dots above and second-line display starts from COM1. The 8 dots of the first line are moved to the lowest edge of the display screen. The output position of the lowest edge depends on the drive duty setting. In vertical smooth scrolling, PS1-PS0 bits can selectively fixed-display only the first to the third lines. Combining these functions enables the fixed display of one line of the lowest edge. For details, see the Partial Smooth Scroll Display Function section.
24
HD66740
Table 10 Common Driver Pin Function
Common Driver Pin Function CN 1-0 = 00 (Normal Output) Common Driver Pin COM1/80 COM2/79 * * COM7/72 COM8/73 COM9/72 COM10/71 * * COM15/66 COM16/65 COM17/64 COM18/63 * * COM24/57 COM25/56 * * COM32/49 COM33/48 * * COM40/41 COM41/40 * * COM48/33 COM49/32 * * COM56/25 COM57/24 * * COM64/17 COM65/16 * * COM72/9 COM73/8 * * COM79/2 COM80/1 CMS = 0 COM1 COM2 * * COM7 COM8 COM9 COM10 * * COM15 COM16 COM17 COM18 * * COM24 COM25 * * COM32 COM33 * * COM40 COM41 * * COM48 COM49 * * COM56 COM57 * * COM64 COM65 * * COM72 COM73 * * COM79 COM80 CMS = 1 COM80 COM79 * * COM74 COM73 COM72 COM71 * * COM66 COM65 COM64 COM63 * * COM57 COM56 * * COM49 COM48 * * COM41 COM40 * * COM33 COM32 * * COM25 COM24 * * COM17 COM16 * * COM9 COM8 * * COM2 COM1 CN 1-0 = 01 (Center Output) CMS = 0 COM65 COM66 * * COM71 COM72 COM73 COM74 * * COM79 COM80 COM1 COM2 * * COM8 COM9 * * COM16 COM17 * * COM24 COM25 * * COM32 COM33 * * COM40 COM41 * * COM48 COM49 * * COM56 COM57 * * COM63 COM64 CMS = 1 COM64 COM63 * * COM58 COM57 COM56 COM55 * * COM50 COM49 COM48 COM47 * * COM41 COM40 * * COM33 COM32 * * COM25 COM24 * * COM17 COM16 * * COM9 COM8 * * COM1 COM80 * * COM73 COM72 * * COM66 COM65 CN1-0 = 10 (Lowest-edge Output) CMS = 0 COM9 COM10 * * COM15 COM16 COM17 COM18 * * COM23 COM24 COM25 COM26 * * COM32 COM33 * * COM40 COM41 * * COM48 COM49 * * COM56 COM57 * * COM64 COM65 * * COM72 COM73 * * COM80 COM1 COM2 * * COM8 CMS = 1 COM8 COM7 * * COM2 COM1 COM80 COM79 * * COM73 COM72 COM71 * * COM66 COM65 COM64 * * COM57 COM56 * * COM49 COM48 * * COM41 COM40 * * COM33 COM32 * * COM25 COM24 * * COM17 COM16 COM15 * * COM9
Double-height Display Control DL3-1: Can be specified when SW = 0. Specify the double-height display for any line. When DL1 = 1, the first line is displayed at double height. When DL2 = 1, the second line is displayed at double
25
HD66740
height. When DL3 = 1, the third line is displayed at double height. Double-height display of multiple lines is possible. For details, see the Double-height Display section. DL6-4: Can be specified when SW = 1. Specify the double-height display for any line. When DL4 = 1, the fourth line is displayed at double height. When DL5 = 1, the fifth line is displayed at double height. When DL6 = 1, the sixth line is displayed at double height. For the seventh to 10th lines, control double-height display by using the DL7-DL10 bits in the display-line control instruction. For details, see the Double-height Display section.
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 0 0 0 DL3 DL2 DL1 DL6 DL5 DL4 (SW = 0) (SW = 1)
Figure 9
Double-height Display Control Instruction
26
HD66740
Vertical Scroll Control 1/2 SN3-0: Set SN2 to SN0 bits when SW = 0. Set the SN3 bit when SW = 1. Specify the display start line output from COM1. Because the CGRAM is assigned a 10-line display area, the data is displayed sequentially from the first line to the 10th line then repeated from the first line again. In partial smooth scrolling, these bits specify the display start line for the next line of the fixed-display line. For details, see the Partial Smooth Scroll Display Function section. SL2-0: Select the top raster-row to be displayed (display-start raster-row) in the display-start line specified by SN2 to SN0. Any raster-row from the first to eighth can be selected (table 12). This function is used to achieve vertical smooth scrolling together with SN2 to SN0. For details, see the Vertical Smooth Scroll section.
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 SN2 SN1 SN0 (SW = 0) <0> <0> SN3 (SW = 1) SL2 SL1 SL0 (SW = 0) <0> PS1 PS0 (SW = 1)
Figure 10 Table 11
SN3 0 0 0 0 0 0 0 0 1 1
Vertical Scroll Control 1/2 Instruction
SN Bits and Display-start Lines
SN2 0 0 0 0 1 1 1 1 0 0 SN1 0 0 1 1 0 0 1 1 0 0 SN0 0 1 0 1 0 1 0 1 0 1 Display-start Line 1st line 2nd line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line 10th line
27
HD66740
Table 12
SL2 0 0 0 0 1 1 1 1
SL Bits and Display-start Raster-row
SL1 0 0 1 1 0 0 1 1 SL0 0 1 0 1 0 1 0 1 Display-start Raster-row 1st raster-row 2nd raster-row 3rd raster-row 4th raster-row 5th raster-row 6th raster-row 7th raster-row 8th raster-row
PS1-0: Specify PS1 to PS0 bits when SW = 1. When PS1-0 = 01, only the first line is fixed-displayed in vertical smooth scrolling, and the other display lines are smooth-scrolled. When PS1-0 = 10, the first and second lines are fixed-displayed. When PS1-0 = 11, the first to third lines are fixed-displayed. For details, see the Partial Smooth Scroll Display Function section. LCD-Driving-Pattern Control B/C: When SW=1 and B/C=0, a B-pattern waveform is generated and alternates in every frame for LCD drivin. When B/C=1, a C-pattern wavefrom is generated and alternates (n-raster-row reversed AC drive) in each raster-row specified by bits EOR and NW4-NW0 in the LCD-driving-waveform control register. For details, see the n-raster-row Reversed AC Drive section. DCC: When SW=1 and DCC=0, a booster operates with the 64-divided clock of the operating frequency. When DCC=1, the booster operates with the 32-divided clock. When the booster operates with the 64-divided clock, current consumptionin the booster is low, but boosting ability is weak.
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 1 1 0 0 DCC B/C (SW = 1)
Figure 10a LCD-Driving-Waveform Control
LCD-Driving-Waveform Control Instruction
EOR: When the C-pattern waveform is set (B/C = 1) and SW = 1 and EOR = 1, the odd/even frame-select signals and the n-raster-row reversed signals are EORed for alternating drive. EOR is used when the LCD is not alternated by combining the set values of the LCD drive duty ratio and n raster-row. For details, see the n-raster-row Reversed AC Drive section. NW4-0: Specify the number of raster-rows n that will alternate at the C-pattern waveform setting (B/C = 1). NW4-NW0 alternate in every set value + 1 raster-row, and the first to the 32nd raster-rows can be selected. When SW = 0, bits NW2, NW1, and NW0 can be set. When SW = 1, bits NW4 and NW3 can be set.
28
HD66740
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 1 1 1 NW2 NW1 NW0 (SW = 0) EOR NW4 NW3 (SW = 1)
Figure 11
LCD-Driving-Waveform Control Instruction
29
HD66740
RAM Address Set AD10-0: Initially set RAM addresses to the address counter (AC). Once the RAM data is written, the AC is automatically updated according to the I/D bit. This allows consecutive accesses without resetting addresses. Once the RAM data is read, the AC is automatically updated according to the I/D bit when RDM = 0, and not updated when RDM = 1. Set RDM to 1 when read, modify, and write are done in every one-byte data. RAM address setting is not allowed in the sleep mode or standby mode.
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 0 1 1 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Figure 12 Table 13
AD10-AD0 "000"H-"06F"H "080"H-"0EF"H "100"H-"16F"H "180"H-"1EF"H "200"H-"26F"H "280"H-"2EF"H "300"H-"36F"H "380"H-"3EF"H "400"H-"46F"H "480"H-"4EF"H
RAM Address Set Instruction
AD Bits and CGRAM Settings
CGRAM Setting Bit map data for COM1 to COM8 Bit map data for COM9 to COM16 Bit map data for COM17 to COM24 Bit map data for COM25 to COM32 Bit map data for COM33 to COM40 Bit map data for COM41 to COM48 Bit map data for COM49 to COM56 Bit map data for COM57 to COM64 Bit map data for COM65 to COM72 Bit map data for COM73 to COM80
Write Data to RAM WD7-0 : Write 8-bit data to the CGRAM. After a write, the address is automatically incremented or decremented by 1 according to the I/D bit setting. During the sleep and standby modes, the CGRAM cannot be accessed.
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0
Figure 13
Write Data to RAM Instruction
30
HD66740
Read Data from RAM RD7-0 : Read 8-bit data from the CGRAM. In the parallel bus interface mode, the first-byte data read will be invalid immediately after the RAM address set, and the consecutive second-byte data will be read normally. In the serial interface mode or I2C bus interface mode, two bytes will be invalid immediately after the start byte, and the consecutive third-byte data will be read normally. For details, see the Serial Data Transfer section. After a RAM read, when RDM = 0, the address is automatically incremented or decremented by 1 according to the I/D bit. When RDM = 1, the address is not updated.
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0
Figure 14
Read Data from RAM Instruction
Address: N set
Start byte
First byte
Dummy read (invalid data)
Address: N set
Second byte
Read (data of address N)
Start byte
Address: N1 (RDM = 0) Address: N (RDM = 1) i) Parallel bus interface mode
First byte
Dummy read (invalid data)
Second byte
Dummy read (invalid data)
Third byte
Read (data of address N)
Address: N1 (RDM = 0) Address: N (RDM = 1) ii) Serial interface mode
Figure 15
RAM Read Sequence
31
HD66740
Table 14 Instruction List
Code
R/W RS 0 0 0 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description 0 0 0 0 0 0 0 0 0 0 0 1 1 1 Execution Cycle
Register Name Start oscillation Driver output control
Starts the oscillation standby -- mode.
CMS SGS Selects the common driver 0 shift direction (CMS) and segment driver shift direction (SGS).
Power control
0
0
0
0
0
0
1
AMP SLP STB Turns on LCD power supply 0 (AMP), and sets the sleep mode (SLP) and standby mode (STB). SW CT4 CT3 Sets the register selection (SW) or upper contrast adjustment bits (CT4-3). BT1 0
Contrast control 1 0
0
0
0
0
1
0
BT0 Sets the register selection 0 (SW) or boost level (BT1/0). 0 0
Contrast control 2 0
0
0
0
0
1
1
CT2 CT1 CT0 Sets the lower contrast adjustment bits (CT2-0). BS2 BS1 BS0 Sets the LCD bias value (BS2-0).
Entry mode set
0
0
0
0
1
0
0
REV I/D
1
Sets the black-and-white 0 reversal (REV) and address update direction after RAM access (I/D). Sets the higher contrast adjustment bit (CT5) and read modify write (RDM). 0
CT5 RDM 0
32
HD66740
Table 14 Instruction List (cont)
Code
R/W RS 0 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description 0 0 1 1 0 D
DL10 0
Register Name Display on/off control
Execution
Cycle 0 Sets display on (D) and double-height display line (DL10).
DL9 DL8 DL7 Specifies double-height display lines (DL9-DL7). Display line control 0 0 0 0 1 1 1 NL2 NL1 NL0 Sets the number of display lines (NL2-0).
0 0
CN1 CN0 NL3 Specifies centering (CN1-0) 0 or the number of display lines (NL3). Double-height display control 0 0 0 1 0 0 0 DL3 DL2 DL1 Specifies double-height display lines (DL3-1). DL6 DL5 DL4 Specifies double-height display lines (DL6-4). Vertical scroll control 1 0 0 0 1 0 0 1 SN2 SN1 SN0 Sets the display-start line (SN2-0). <0> <0> SN3 Sets the display-start line (SN3). Vertical scroll control 2 0 0 0 1 0 1 0 0 0 0 0
SL2 SL1 SL0 Sets the display-start raster- 0 row (SL2-0). <0> PS1 PS0 Sets the partial scroll (PS1-0). 0
33
HD66740
Table 14 Instruction List (cont)
Code
R/W RS 0 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description 0 1 1 1 0 0 DCC B/C Selects the boosting cycle (DCC) or LCD drive AC waveform (B/C)
Register Name LCD-drivingpattern control
Execution
Cycle 0
LCD-driving0 waveform control
0
0
1
1
1
1
NW2 NW1 NW0 Sets the number of n-raster- 0 rows (NW2-0) in C-pattern AC drive. EOR NW4 NW3 Sets the EOR output (EOR) or the number of n-rasterrows (NW4-3) in C-pattern AC drive. 0
RAM address set 0 (upper bits) RAM address set 0 (lower bits) Write data to RAM 0 Read data from RAM 1
0
1
0
1
AD10-6 (upper bits) AD5-0 (lower bits) Write data Read data
Initially sets the upper 0 addresses of the RAM to the address counter (AC). Initially sets the lower 0 addresses of the RAM to the AC. Writes data to CGRAM. Reads data from CGRAM. 0 0
0
1
1
1 1
Notes: 1.
The upper column of each register can be set when SW = 0. when SW = 1.
The lower column can be set
34
HD66740
Bit definition: CMS = 0: COM1/80 => COM1 SGS = 0: SEG1/112 => SEG1 AMP = 1: Operational amplifier and booster circuit on SLP = 1: Sleep mode STB = 1: Standby mode SW = 0: Upper register setting SW = 1: Lower register setting CT5-0: Contrast adjustment BT1-0: Boost level selection (00: Triple, 01: Quadruple, 10: Five-times) BS2-0: LCD drive bias selection REV = 0: Normal display REV = 1: Black-and-white reversed display of the graphics display ID = 1: Address increment ID = 0: Address decrement RDM = 1: Read, modify, and write mode (Not automatically update the address counter after reading) D = 1: Display on NL3-0: Display line setting (0000: 1/8 duty ratio, 0001: 1/16 duty ratio, 0010: 1/24 duty ratio, 0011: 1/32 duty ratio, 0100: 1/40 duty ratio, 0101: 1/48 duty ratio, 0110: 1/56 duty ratio, 0111: 1/64 duty ratio, 1000: 1/72 duty ratio, 1001: 1/80 duty ratio) DL1-10: Double-height line specifications (DL1: 1st line, DL2: 2nd line, DL3: 3rd line, DL4: 4th line, DL5: 5th line, DL6: 6th line, DL7: 7th line, DL8: 8th line, DL9: 9th line, DL10: 10th line) SN3-0: Display-start line (0000: 1st line, 0001: 2nd line, 0010: 3rd line, 0011: 4th line, 0100: 5th line, 0101: 6th line, 0110: 7th line, 0111: 8th line, 1000: 9th line, 1001: 10th line) SL2-0: Display-start raster-row specifications (000: 1st raster-row...111: 8th raster-row) CN1-0 Centering specifications (00: no centering, 01: 16-dot shift below, 10: 8-dot shift above) B/C = 0: B-pattern waveform drive B/C = 1: C-pattern waveform drive EOR = 1: EOR alternating drive at C-pattern waveform NW4-0: Reversed number of n raster-rows at C-pattern waveform drive (alternating with the set value + one raster-row) DCC = 0: Boosted at 1/64-divided clock DCC = 1: Boosted at 1/32-divided clock AD10-0: CGRAM address set (CGRAM: 000H-4EFH)
35
HD66740
Reset Function
The HD66740 is internally initialized by RESET input. The reset input must be held for at least 1 ms. Instruction Set Initialization: Start oscillation executed Driver output control (SGS = 0, CMS = 0) Power control (AMP = 0: LCD power off, SLP = 0: Sleep mode off, STB = 0: Standby mode off) Three times boost (BT1/0 = 00), 1/10 bias drive (BS2/1/0 = 000), Weak contrast (CT5-0 = 00000) Entry mode set (REV = 0: Normal display, I/D = 1: Increment by 1, RDM = 0: Automatically update after reading) 6. Display on/off control (D = 0: Display off, CEN = 0: Normal position) 7. Display line control (NL3/2/1/0 = 1001: 1/80 duty ratio) 8. Double-height display off (DL10-1 = 0000000000) 9. Vertical scroll control (SN3/2/1/0 = 0000: First line displayed at the top, SL2/1/0: First raster-row displayed at the top of the first line, PS1/0 = 00: Partial scroll off) 10. 1/64-divided clock boost (DCC = 0) 11. B-pattern waveform AC drive (B/C = 0, EOR = 0, NW4/3/2/1/0 = 00000) RAM Data Initialization: 1. CGRAM This is not automatically initialized by reset input but must be initialized by software while display is off (D = 0). Output Pin Initialization: 1. LCD driver output pins (SEG/COM): Outputs GND level 2. Booster output pins (VLOUT): Outputs GND level 3. Oscillator output pin (OSC2): Outputs oscillation signal 1. 2. 3. 4. 5.
36
HD66740
Serial Data Transfer (Clock synchronized serial interface)
Setting the IM1 and IM2 pins (interface mode pins) to the GND level allows standard clock-synchronized serial data transfer, using the chip select line (CS*), serial data line (SDA), and serial transfer clock line (SCL). For a serial interface, the IM0/ID pin function uses an ID pin. The HD66740 initiates serial data transfer by transferring the start byte at the falling edge of CS* input. It ends serial data transfer at the rising edge of CS* input. The HD66740 is selected when the 6-bit chip address in the start byte transferred from the transmitting device matches the 6-bit device identification code assigned to the HD66740. The HD66740, when selected, receives the subsequent data string. The least significant bit of the identification code can be determined by the ID pin. The five upper bits must be 01110. Two different chip addresses must be assigned to a single HD66740 because the seventh bit of the start byte is used as a register select bit (RS): that is, when RS = 0, an instruction can be issued, and when RS = 1, data can be written to or read from RAM. Read or write is selected according to the eighth bit of the start byte (R/W bit) as shown in table 16. After receiving the start byte, the HD66740 receives or transmits the subsequent data byte-by-byte. The data is transferred with the MSB first. Two bytes of RAM read data after the start byte are invalid. The HD66740 starts to read correct RAM data from the third byte. Table 15
Transfer Bit Start byte format
Start Byte Format
S Transfer start 1 2 3 4 5 6 7 RS 1 0 ID 8 R/W
Device ID code 0 1 1
Note: ID bit is selected by the IM0/ID pin.
Table 16
RS 0 0 1 1 R/W 0 1 0 1
RS and R/W Bit Function
Function Writes instruction Writes RAM data Reads RAM data
37
HD66740
a) Basic Data-transfer Timing through Clock-synchronized Serial Bus Interface Transfer start CS* (Input) 1 SCL (Input) SDA (Input/ output) MSB "0" "1" "1" "1" "0" ID LSB RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RS R/W Instruction, RAM data 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Transfer end
Device ID code Start byte
b) Consecutive Data-transfer Timing through Clock-synchronized Serial Bus Interface CS* (Input) SCL (Input) SDA (Input/ output) Start 12345678 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Start byte
Instruction 1
Instruction 2 Instruction 1 execution time
Instruction 3 Instruction 2 execution time End
Note: When instruciton 1 is a clear display instruction, adjust the transfer rate so that the 8th bit of instruction 2 is transferred after execution of the clear display instruction. c) RAM Data Read-transfer Timing CS* (Input) 12345678 SCL (Input) SDA (Input/ output) Start Note: Two bytes of the RAM read data after the start byte are invalid. The HD66740 starts to read the correct RAM data from the third byte. Start byte RS = 1, R/W = 1 End Dummy read 1 Dummy read 2 RAM data read 1 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 16
Clock-synchronized Serial Interface Timing Sequence
38
HD66740
Serial Data Transfer (I2C bus interface)
Setting the IM2=Vcc and IM1=GND level allows I2C bus interface, using the serial data line (SDA) and serial transfer clock line (SCL). For the I2C bus interface, the IM0/ID pin function uses an ID pin. The HD66740W is initiated serial data transfer by transferring the first byte when a high SCL level at the falling edge of the SDA input is sampled; it ends serial data transfer when a high SCL level at the rising edge of the SDA input is sampled. Table 16-a illustrates the start byte of I2C bus interface data and Figure 16-a and 16-b show the I2C bus interface timing sequence. The HD66740W is selected when the higher 6-bit slave address in the first byte transferred from the master device match the 6-bits device identification code assigned to the HD66740W. The HD66740W, when selected, receive the subsequent data string. The lower 1-bit of the device identification code can be determined by the ID pin; select an appropriate code that is not assigned to any other slave device. The upper five bits are fixed to 01110. One slave address is assigned to a single HD66740W. The ninth bit of the first byte is a receive-data acknowledge bit (ACK). When the received slave address matches the device ID code, HD66740W pulls down the ACK bit to a low level. Therefore, the ACK output buffer is an open-drain structure, only allowing low-level output. However, the ACK bit is undermined immediately after power-on; make sure to initialize the LSI using the RESET* input. After identifying the address in the first byte, the HD66740W receives the subsequent data as an HD66740W instruction or as RAM data. Having received 8-bit data normally, HD66740W pulls down the ninth bit (ACK) to a low level. The instruction or RAM data is 8-bits data format. Two bytes of RAM read data after the start byte are invalid. The HD66740W start to read correct RAM data from third byte. Table 16-a Start Byte Format
Transfer Bit Start byte format S Transfer start 0 Note: ID bit is selected by the IM0/ID pin. 1 1 2 3 4 5 6 7 RS 0 ID 8 R/W 9 ACK
Device ID code 1 1
Table 16-b RS and R/W bit function
RS 0 0 1 1 R/W 0 1 0 1 Function Writes instruction Writes RAM data Reads RAM data
39
HD66740
a) Basic data-receive timing through the I2C bus interface
Transfer start 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Transfer end
SCL (input)
SDA (input/ output)
"0" "1" "1" "1" "0" ID RS "0" Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack
Device ID code RS RW
Start byte
Acknowledge
Instruction / RAM data Acknowledge
b) Consecutive data-receive timing through the I2C bus interface
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
SCL
ACK
ACK
ACK
ACK
SDA
S
Start byte
Instruction or RAM write
Instruction or RAM write
Instruction or RAM write
Instruction or RAM write
ACK
P Transfer end
Transfer start
Instruction / RAM write execution.
Instruction / RAM write execution.
Instruction / RAM write execution.
Instruction / RAM write execution.
note: - Start byte should be transfered just after start (S).
Figure 16-a
I2C bus interface data-receive sequence
a) Basic data-send timing through the I2C bus interface
Transfer start 1 2 3 4 5 6 7 8 9 Transfer end 10 11 12 13 14 15 16 17 18
SCL (input)
SDA (input/ output)
"0" "1" "1" "1" "0" ID
"1" "1" Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack
Device ID code RS RW
Start byte
Acknowledge
RAM read
Acknowledge
b) Consecutive data-send timing through the I2C bus interface
SCL
ACK
ACK
ACK
ACK
SDA
S
Start byte
Dummy read (1 byte)
RAM data read
RAM data read
ACK
RAM data read
P
Transfer start
Transfer end
note: - Start byte should be transfered just after start (S).
Figure 16-b
I2C bus interface data-send sequence
40
HD66740
Parallel Data Transfer
8-bit Bus Interface Setting the IM2/1/0 (interface mode) to the GND/Vcc/GND level allows E-clock-synchronized 8-bit parallel data transfer. Setting the IM2/1/0 (interface mode) to the Vcc/Vcc/GND level allows 80system 8-bit parallel data transfer. When the number of buses or the mounting area is limited, use a 4bit bus interface or serial data transfer.
*Interface via I/O port C0 C1 C2 A0-A7 8 E/WR* RS HD66740 R/W / RD* (CS*) DB0-DB7
H8/325
Figure 17 4-bit Bus Interface
Interface to 8-bit Microcomputer
Setting the IM2/1/0 (interface mode) to the GND/Vcc/Vcc level allows E-clock-synchronized 4-bit parallel data transfer using pins DB7-DB4. Setting the IM2/1/0 (interface mode) to the Vcc/Vcc/Vcc level allows 80-system 4-bit parallel data transfer. The 8-bit instructions and RAM data are divided into four upper/lower bits and the transfer starts from the upper four bits. Note: Transfer synchronization function for a 4-bit bus interface The HD66740 supports the transfer synchronization function which resets the upper/lower counter to count upper/lower 4-bit data transfer in the 4-bit bus interface. Noise causing transfer mismatch between the four upper and lower bits can be corrected by a reset triggered by consecutively writing a 0000 instruction four times. The next transfer starts from the upper four bits. Executing synchronization function periodically can recover any runaway in the display system.
RS
R/W
E DB7- DB4 "0000" (1) "0000" (2) "0000" (3) "0000"
Upper Lower
Upper/ lower
(4) (4-bit transfer synchronization)
Figure 18
4-bit Transfer Synchronization
41
HD66740
Oscillation Circuit
The HD66740 can either be supplied with operating pulses externally (external clock mode) or oscillate using an internal R-C oscillator with an external oscillator-resistor (external resistor oscillation mode). Note that in R-C oscillation, the oscillation frequency is changed according to the internal capacitance value, the external resistance value, or operating power-supply voltage. Insert the dumping registance of about 1.5k to prevent malfunctions caused by over-shoot or under-shoot noise in the external clock mode.
1) External clock mode 2) External resistor oscillation mode The oscillator frequency can be 1.5 k Clock (80 kHz) OSC1 HD66740 Rf OSC2 HD66740 OSC1 adjusted by oscillator resistor (Rf). If Rf is increased or power supply voltage is decreased, the oscillation frequency decreases. For the relationship between Rf resistor value and oscillation Insert the dumping resistance. frequency, see the Electric Characteristics Notes section.
Figure 19 Table 17
Oscillation Circuits
Relationship between Drive Duty Ratio and Frame Frequency (fosc = 75 kHz)
Display mode 1-line Display 2-line Display 3-line Display 4-line Display 5-line Display 6-line Display 7-line Display 8-line Display 9-line Display 10-line Display
Set value for NL3-0 LCD Drive Multiplexing duty ratio Drive bias (recommended value) Frame frequency One-frame frequency 0000 1/8 1/4 0001 1/16 1/5 0010 1/24 1/6 0011 1/32 1/6 0100 1/40 1/7 0101 1/48 1/8 0110 1/56 1/8 0111 1/64 1/9 1000 1/72 1/9.5 1001 1/80 1/10
73 Hz 1,024
73 Hz 1,024
73 Hz 1,032
73 Hz 1,024
72 Hz 1,040
74 Hz 1,008
74 Hz 1,008
73 Hz 1,024
65 Hz 1,152
59 Hz 1,280
Note: If the frame frequency is low and the display flickers, increase the oscillation frequency (fosc). Particularly in the 9-line display and 10-line display modes, note that the frame frequency is lowered.
42
HD66740
1
V1 V2 COM1 V5 GND V1 V2
COM2 V5 GND V1 V2
COM79 V5 GND V1 V2
COM80 V5 GND
2
3
4
79
80
1
2
3
79
80
1 frame
1 frame
Figure 20
LCD Drive Output Waveform (B-pattern AC Drive with 1/80 Multiplexing Duty Ratio)
43
HD66740
n-raster-row Reversed AC Drive
The HD66740 supports not only the LCD reversed AC drive in a one-frame unit (B-pattern waveform) but also the n-raster-row reversed AC drive which alternates in an n-raster-row unit from one to 32 raster-rows (C-pattern waveform). When a problem affecting display quality occurs, such as crosstalk at high-duty driving of more than five lines (1/40 duty), the n-raster-row reversed AC drive (C-pattern waveform) can improve the quality. Determine the number of raster-rows n (NW bit set value + 1) for alternating after confirmation of the display quality with the actual LCD panel. However, if the number of AC raster-rows is reduced, the LCD alternating frequency becomes high. Because of this, the charge or discharge current is increased in the LCD cells.
1 frame
1 frame
1 2 3 4 5 6 7 8 9 10 11 12 13
79 80 1 2 3 4 5 6 7 8 9 10 11 12 13
79 80 1 2 3
B-pattern waveform drive * 1/80 duty
C-pattern waveform drive * 1/80 duty * 11-raster-row reversal * Without EORs C-pattern waveform drive * 1/80 duty * 11-raster-row reversal * With EORs Note: Specify the number of AC drive raster-rows and the necessity of EOR so that the DC bias is not generated for the liquid crystal.
Figure 21
Example of an AC Signal under n-raster-row Reversed AC Drive
44
HD66740
Liquid Crystal Display Voltage Generator
When External Power Supply and Internal Operational Amplifiers are Used To supply LCD drive voltage directly from the external power supply without using the internal booster, circuits should be connected as shown in figure 22. Here, contrast can be adjusted by software through the CT bits of the contrast adjustment register. The HD66740 incorporates a voltage-follower operational amplifier for each V1 to V5 to reduce current flowing through the internal bleeder-resistors, which generate different levels of liquid-crystal drive voltages. Thus, potential differences between VLCD and V1 and between V5 and GND must be 0.4 V or higher. Note that the OPOFF pin must be grounded when using the operational amplifiers. Place a capacitor of about 0.1 F to 0.5 F between each internal operational amplifier V1OUT to V5OUT output and GND and stabilize the output level of the operational amplifier. OPOFF = GND VLCD
VLCD VR V1OUT R V2OUT R0 V3OUT R 0.1 F to 0.5 F V4OUT R V5OUT GND Vci C1+ C1C2+ C2C3+ C3C4+ C4VLOUT R GND
+ + + + + -
HD66740
V1
V2 LCD driver V3 V4
SEG1 to SEG112
COM1 to COM80
V5
+++++ GND
Booster
Figure 22
External Power Supply Circuit for LCD Drive Voltage Generation
45
HD66740
When an Internal Booster and Internal Operational Amplifiers are Used To supply LCD drive voltage using the internal booster, circuits should be connected as shown in figure 23. Here, contrast can be adjusted through the CT bits of the contrast control instruction. Temperature can be compensated either through the CT bits or by controlling the reference voltage for the booster (Vci pin) using a thermistor. Note that Vci is both a reference voltage and power supply for the booster. The reference voltage must therefore be adjusted using an emitter-follower or a similar element so that sufficient current can be supplied. In this case, Vci must be equal to or smaller than the VCC level. The HD66740 incorporates a voltage-follower operational amplifier for each of V1 to V5 to reduce current flowing through the internal bleeder-resistors, which generate different liquid-crystal drive voltages. Thus, the potential differences between VLCD and V1 and between V5 and GND must be 0.4 V or higher. Note that the OPOFF pin must be grounded when using the operational amplifiers. Place a capacitor of about 0.1 F to 0.5 F between each internal operational amplifier V1OUT to V5OUT output and GND and stabilize the output level of the operational amplifier.
46
HD66740
OPOFF = GND
VLCD VR V1OUT R V2OUT R0 V3OUT R 0.1 F to 0.5 F V4OUT R V5OUT GND Vci 1 F R GND
+ + + + + -
HD66740
V1
V2 LCD driver V3 V4
SEG1 to SEG112
COM1 to COM80
V5
+++++ GND Vci +
C1+ C1-
1 F
+
C2+ C2-
Booster
1 F
+ +
C3+ C3C3+ C3VLOUT
1 F
+
1 F
GND Notes: 1. The reference voltage input (Vci) must be adjusted so that the output voltage after boosting will not exceed the absolute maximum rating for the liquid-crystal power supply voltage (17 V). Particularly, Vci must be 3.3 V or less for five-times boosting. 2. Vci is both a reference voltage and power supply for the booster; connect it to Vcc directly or combine it with a transistor so that sufficient current can be obtained. 3. Polarized capacitors must be connected correctly. 4. Circuits for temperature compensation should be based on the sample circuit in figure 24.
Figure 23
Internal Booster for LCD Drive Voltage Generation
HD66740 Vcc Vcc
Thermistor
Tr
Vci
GND
Figure 24
Temperature Compensation Circuit
47
HD66740
Notes on Using Internal Operational Amplifier The HD66740 has a low-current-consumption-type operational amplifier. When a low-voltage supply is used, particularly at low temperatures near -20C, the current in the operational amplifier is reduced. Therefore, depending on the specifications or display pattern of the LCD panel used, screen quality may be poor or the LCD panel may not operate at all. For the operational specifications of the LCD panel, one must consider the drive condition (setting of the VTEST pin) or the peripheral circuits of the LCD panel in conjunction with the power-supply voltage. Pin condition for HD66740 (setting VTEST pin): 1. When the power-supply voltage is Vcc 2.5 V (i.e., the current in the operational amplifier is sufficient), leave the VTEST pin open (disconnected). 2. When the power-supply voltage is Vcc < 2.5 V (i.e., the current is reduced in the operational amplifier at low temperature), 1.2 to 1.3 V should be input to the VTEST pin. The following table and figure correspond to inputs of 1.2 to 1.3 V to the VTEST pin. When higher LCD drive current is required due to the characteristics of the LCD panel, check the screen quality and current consumption, adjust the resistance values (R1 and R2), and increase the VTEST pin voltage. (This is also valid when Vcc 2.5 V.)
Vcc R1 to VTEST pin R2 GND Vtest = 1.2 to 1.3V
Figure 24-a Table 17-a
Vcc 2.4 V 2.0 V 1.8 V
Circuit to for Generating VTEST Pin Voltage
Settings to Generate VTEST Pin Voltage
R1 270 k 220 k 180 k R2 330 k 360 k 390 k Vtest (VTEST Pin Voltage) 1.23 V 1.22 V 1.22 V
48
HD66740
Countermeasures for Screen Quality when Using On-chip Operational Amplifier The HD66740 is an on-chip LCD driver that has an LCD power supply for high duty. Screen quality is affected by the load current of the high-duty LCD panel used. When the bias (1/10 bias, 1/9.5 bias, 1/9 bias, etc.) is high and the displayed pattern is completely or almost completely white, the white sections may appear dark. If this happens, execute the following countermeasures to improve screen quality. (1) After the change in the V4OUT/V3OUT level is verified, insert about 1 M between V4OUT and GND or VLCD and V3OUT and then adjust the screen quality (see the following figures). By inserting resistance, the current consumption increases as much as the boosting factor of the resistance current. Adjust the resistance after checking the screen quality and the increase in current consumption. (2) Decrease the drive bias and use the new bias level after verifying that the potential differences between V4OUT and GND or VLCD and V3OUT are sufficient.
VLCD
Driver V4OUT Fixed current source
Vbn
C
RV4
GND
Figure 24-b
Countermeasure for V4OUT Output
VLCD
Vbp
Fixed current source
RV3
V3OUT Driver C
GND
Figure 24-c Note:
Countermeasure for V3OUT Output
The actual LCD drive voltage-VLCD used must not exceed 15.0 V, and the absolute rating must not exceed 16.0 V.
49
HD66740
Switching the Boosting Multiplying Factor Instruction bits (BT1/0 bits) can optionally select the boosting multiplying factor of the internal booster. According to the display status, power consumption can be reduced by changing the LCD drive duty and the LCD drive bias, and by controlling the boosting multiplying factor for the minimum requirements. For details, see the Partial-display-on Function section. Due to the maximum boosting multiplying factor, the following external capacitor needs to be connected. For example, when the maximum boosting is quadrupled, the capacitors between C4+ and C4- for fivetimes boosting are not needed, so these pins must be open. Table 18
BT1 0 0 1 1
VLOUT Output Status
BT0 0 1 0 1 VLOUT Output Status Triple boosting output Quadruple boosting output Five-times boosting output Setting inhibited
i) Maximum five-times boosting
ii) Maximum quadruple boosting
Vci
0.47 F + to 1 F 0.47 F + to 1 F 0.47 F + to 1 F
iii) Maximum triple boosting
Vci
0.47 F + to 1 F 0.47 F + to 1 F
Vci
0.47 F + to 1 F
0.47 F + to 1 F
0.47 F + to 1 F
0.47 F + to 1 F
Vci C1+ C1C2+ C2C3+ C3C4+ C4-
Vci C1+ C1C2+ C2C3+ C3C4+ C41 F
Vci C1+ C1C2+ C2C3+ C3C4+ C41 F
1 F
+
VLOUT
+
VLOUT
+
VLOUT
GND
GND
GND
Figure 25
Booster Output Multiplying Factor Switching
50
HD66740
Example of Power-supply Voltage Generator for More Than Five-times Boosting Output The HD66740 incorporates the booster for up to five-times boosting. However, the LCD drive voltage (VLCD) will not be enough for five-times boosting from Vcc when the power-supply voltage of Vcc is low or when the LCD drive voltage is high for the high-contrast LCD display. In this case, the reference voltage (Vci) for boosting can be set higher than the power-supply voltage of Vcc. Set the Vci input voltage for the booster to 3.6 V or less within the range of Vcc + 1.0 V. Control the Vci voltage so that the boosting output voltage (VLOUT) should be less than the absolute maximum ratings (17 V).
HD66740
Regula -tor (1)
2.5 V
Vcc
Logic circuit
Battery 3.6 V
C1+ Regula -tor (2)
+ + + +
1 F 1 F 1 F 1 F
3.0 V
Vci
C1C2+
Booster
GND
C2C3+
3.0 x 5 = 15 V
VLCD (= 15 V)
C3VLOUT C4+ C4SEG1 to SEG112
1 F
+
VLCD
LCD driver
COM1 to COM80 GND
GND
GND Vcc (= 3 V) Vcc (= 2.5 V) GND (= 0 V)
Figure 26
Usage Example of Booster at Vci > Vcc
51
HD66740
Contrast Adjuster
Software can adjust 64-step contrast for an LCD by varying the liquid-crystal drive voltage (potential difference between VLCD and V1) through the CT bits of the contrast adjustment register (electron volume function). The value of a variable resistor between VLCD and V1 (VR) can be precisely adjusted in a 0.05 x R unit within a range from 0.05 x R through 3.20 x R, where R is a reference resistance obtained by dividing the total resistance. The HD66740 incorporates a voltage-follower operational amplifier for each of V1 to V5 to reduce current flowing through the internal bleeder resistors, which generate different liquid-crystal drive voltages. Thus, CT5-0 bits must be adjusted so that the potential differences between VLCD and V1 and between V5 and GND are 0.4 V or higher when liquid-crystal drives, particularly when the VR is small.
HD66740
VLCD VR R R R0 R R GND
+ + + + + -
CT V1 V2 V3
V4 V5 GND
Figure 27
Contrast Adjuster
52
HD66740
Table 19 Contrast Adjustment Bits (CT) and Variable Resistor Values
CT Set Value
CT5 CT4 CT3 CT2 CT1 CT0
Variable Resistor Potential Difference between V1 and GND Value (VR) 3.20 x R 3.15 x R 3.10 x R 3.05 x R 3.00 x R 2.95 x R 2.90 x R 2.85 x R 2.80 x R 2.75 x R 2.70 x R 2.65 x R 2.60 x R
Display Color
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1
0 0 1 1 0 0 1 1 0 0 1 1 0
0 1 0 1 0 1 0 1 0 1 0 1 0
(Small)
(Light)
0 1 1 1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0 0 1 1
1 0 0 0 0 1 1 1 1 0 0
1 0 0 1 1 0 0 1 1 0 0
1 0 1 0 1 0 1 0 1 0 1
1.65 x R 1.60 x R 1.55 x R 1.50 x R 1.45 x R 1.40 x R 1.35 x R 1.30 x R 1.25 x R 1.20 x R 1.15x R
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
0 0 1 1
0 1 0 1
0.20 x R 0.15 x R 0.10 x R 0.05 x R
(Large)
(Deep)
53
HD66740
Table 20
Bias
Contrast Adjustment per Bias Drive Voltage
LCD drive voltage: VDR
- LCD drive voltage adjustment range
Contrast adjustment range : 0.757 x (VLCD-GND) VDR 0.995 x (VLCD-GND)
1/10 bias drive
10 x R x (VLCD - GND) 10 x R + VR
R - Limit of potential x (VLCD-GND) 0.4 [V] : 10 x R + VR difference between V5 and GND VR - Limit if potential x (VLCD-GND) 0.4 [V] : difference between VLCD and V1 10 x R + VR
- LCD drive voltage adjustment range
: 0.748 x (VLCD-GND) VDR 0.994 x (VLCD-GND)
1/9.5 bias drive
9.5 x R x (VLCD - GND) 9.5 x R + VR
R - Limit of potential x (VLCD-GND) 0.4 [V] : difference between V5 and GND 9.5 x R + VR VR - Limit if potential x (VLCD-GND) 0.4 [V] : difference between VLCD and V1 9.5 x R + VR
- LCD drive voltage adjustment range
: 0.737 x (VLCD-GND) VDR 0.994 x (VLCD-GND) :
1/9 bias drive
9xR 9 x R + VR
x (VLCD - GND) - Limit of potential
R x (VLCD-GND) 0.4 [V] 9 x R + VR VR - Limit if potential x (VLCD-GND) 0.4 [V] : difference between VLCD and V1 9 x R + VR
difference between V5 and GND - LCD drive voltage adjustment range
: 0.714 x (VLCD-GND) VDR 0.993 x (VLCD-GND) R x (VLCD-GND) 0.4 [V] 8 x R + VR VR x (VLCD-GND) 0.4 [V] 8 x R + VR
1/8 bias drive
8xR x (VLCD - GND) 8 x R + VR
- Limit of potential : difference between V5 and GND
1/7 bias drive
- Limit if potential : difference between VLCD and V1 - LCD drive voltage : 0.686 x (VLCD-GND) VDR 0.993 x (VLCD-GND) adjustment range
7xR x (VLCD - GND) 7 x R + VR
R - Limit of potential x (VLCD-GND) 0.4 [V] : 7 x R + VR difference between V5 and GND VR - Limit if potential x (VLCD-GND) 0.4 [V] : difference between VLCD and V1 7 x R + VR
- LCD drive voltage adjustment range
: 0.652 x (VLCD-GND) VDR 0.992 x (VLCD-GND) R x (VLCD-GND) 0.4 [V] 6 x R + VR VR x (VLCD-GND) 0.4 [V] 6 x R + VR
1/6 bias drive
6xR x (VLCD - GND) 6 x R + VR
- Limit of potential : difference between V5 and GND
1/5 bias drive
- Limit if potential : difference between VLCD and V1 - LCD drive voltage : 0.610 x (VLCD-GND ) VDR 0.990 x (VLCD-GND) adjustment range
5xR - Limit of potential : x (VLCD - GND) difference between V5 and GND 5 x R + VR
- Limit if potential : difference between VLCD and V1 - LCD drive voltage adjustment range
R x (VLCD-GND ) 0.4 [V] 5 x R + VR VR x (VLCD-GND ) 0.4 [V] 5 x R + VR
1/4 bias drive
: 0.556 x (VLCD-GND) VDR 0.988 x (VLCD-GND) R x (VLCD-GND) 0.4 [V] 4 x R + VR VR x (VLCD-GND) 0.4 [V] 4 x R + VR
4xR x (VLCD - GND) 4 x R + VR
- Limit of potential : difference between V5 and GND - Limit if potential : difference between VLCD and V1
54
HD66740
Liquid Crystal Display Drive Bias Selector
An optimum liquid crystal display bias value can be selected using BS2-0 bits, according to the liquid crystal drive duty ratio setting (NL3-0 bits). Liquid crystal display drive duty ratio and bias value can be displayed while switching software applications to match the LCD panel display status. The optimum bias value calculated using the following expression is an ideal value where the optimum contrast is obtained. Driving by using a lower value than the optimum bias value provides lower contrast and lower liquid crystal display voltage (potential difference between V1 and GND). When the liquid crystal display voltage is insufficient even if a five-times booster is used or output voltage is lowered because the battery life has been reached, the display can be made easier to see by lowering the liquid crystal bias. The liquid crystal display can be adjusted by using the contrast adjustment register (CT4-0 bits) and selecting the booster output level (BT1/0 bits). Optimum bias value for 1/N duty ratio drive voltage = Table 21
LCD drive duty ratio (NL3-0 set value) Optimum drive bias value (BS2-0 set value) 1/80 1001 1/10 000 1/72 1000 1/9.5 001 1/64 0111 1/9 010
1 N+1
Optimum Drive Bias Values
1/56 0110 1/8 011 1/48 0101 1/8 011 1/40 0100 1/7 100 1/32 0011 1/6 101 1/24 0010 1/6 101 1/16 0001 1/5 110 1/8 0000 1/4 111
55
HD66740
VLCD VLCD VLCD VLCD VLCD
VR V1 R V2 R V3 6R V4 R V5 R GND
VR V1 R V2 R V3 5.5R R V5 R GND
VR V1 R V2 R V3 5R V4 R V5 R GND V4
VR V1 R V2 R V3 4R R V5 R GND
VR V1 R V2 R V3 3R V4 R V5 R GND V4
GND i) 1/ 10 bias (BS2-0 = 000) VLCD
GND ii) 1/ 9.5 bias (BS2-0 = 001) VLCD
GND iii) 1/ 9 bias (BS2-0 = 010)
GND iv) 1/ 8 bias (BS2-0 = 011)
GND v) 1/7 bias (BS2-0 = 100)
VLCD VR V1 R V2 R V3 2R V4 R V5 R GND R R V5 GND R R V4 R V3 R R V5 GND Note: R = Reference resistor R V2 R VR V1 VR V1 V2 V3,V4
GND v) 1/6 bias (BS2-0 = 101)
GND v) 1/5 bias (BS2-0 = 110)
GND vi) 1/ 4 bias (BS2-0 = 111)
Figure 28
Liquid Crystal Display Drive Bias Circuit
56
HD66740
LCD Panel Interface
The HD66740 has a function for changing the common driver/segment driver output shift direction using the CMS bit and SGS bit to meet the chip mounting positions of the HD66740. This is to facilitate the interface wiring to the LCD panel with COG or TCP installed.
HITACHI Ltd. LCD Controller/ Driver:HD66740 >112 x 80 dots Graphisc display >16 x 10 chracter display > >x4 Booster >Op-amp
SEG112/1 COM72/9 SEG1/112 COM80/1
COM73/8 COM40/41
HITACHI Ltd. LCD Controller/ Driver:HD66740 >112 x 80 dots Graphisc display >16 x 10 chracter display > >x4 Booster >Op-amp
SEG1/112 COM80/1
COM73/8 COM40/41
32 8
COM41/40 COM8/73 COM1/80
Front of chip
* CMS = 0 * SGS = 1
8 32
8 32
Back of chip
* CMS = 0 * SGS = 0
SEG112/1 COM72/9
32
COM41/40 COM8/73 COM1/80
COM9/72
COM9/72
8
COM8/72
COM1/80
32 8
COM40/41 COM73/8 COM80/1 SEG1/112
Front of chip
* CMS = 1 * SGS = 0
COM8/73 COM41/40
8 32
8 32
COM1/80
COM8/73 COM41/40
COM9/72
Back of chip
* CMS = 1 * SGS = 1
COM40/41 COM73/8 COM80/1 SEG1/112
32 8
COM72/9 SEG112/1
COM72/9 SEG112/1
HITACHI Ltd. LCD Controller/ Driver:HD66740 >112 x 80 dots Graphisc display >16 x 10 chracter display > >x4 Booster >Op-amp
Figure 29
HITACHI Ltd. LCD Controller/ Driver:HD66740 >112 x 80 dots Graphisc display >16 x 10 chracter display > >x4 Booster >Op-amp
1/80 Duty Drive Pattern Wiring
57
HD66740
LCD PANEL
SEG112/1 COM72/9 SEG1/112 COM80/1 COM73/8 COM40/41
Front of chip
* CMS = 0 * SGS = 1
COM41/40 COM8/73 COM1/80
COM9/72
Figure 30 Table 22
1-line Display Pattern Wiring
Number of Left and Right Extension Lines of Common Driver
Left Edge of Screen 16 (COM1-8, 41-48) 24 (COM1-8, 41-56) 32 (COM1-8, 41-64) 40 (COM1-8, 41-72) 40 (COM1-8, 41-72) Right Edge of Screen 32 (COM9-40) 32 (COM9-40) 32 (COM9-40) 32 (COM9-40) 40 (COM9-40, 73-80)
Drive Duty Ratio 1/48 1/56 1/64 1/72 1/80
58
HD66740
Graphics Display Function
In the graphics display mode, kanji characters, special symbols, and graphics icons can be displayed. Up to 112 x 80-dot display is allowed using the CGRAM. Thus, for a 12 x 13-dot kanji font, up to a 6-line x 9-character kanji display, and for a 14 x 15-dot kanji font, up to a 6-line x 8-character kanji display, and for a 16 x 16-dot kanji font, up to a 5-line x 6-character kanji display are allowed.
i) 12 x 13-dot kanji display example (6-line x 9-character display)
ii) 112 x 80-dot game display example
Figure 31
Display Example in Graphics Display Mode
Vertical Smooth Scroll Display
The HD66740 can scroll character and graphics display vertically in units of raster-rows. This is achieved by writing display data into a one-line area that is not being used for display. In other words,
59
HD66740
one line can be used to achieve continuous smooth vertical scroll even in a 9-line or less display. Here, after the 10th line is displayed, the first line is displayed again. When the 10th line is fully displayed, all one-line display data must be rewritten immediately after scrolling because there is no non-displayed area. Additionally, when display areas of a graphics icon such as a pictogram or a menu bar are partially fixed-displayed, the remaining areas can be displayed. For details, see the Partial Smooth Scroll Display Function section. Specifically, this function is controlled by incrementing or decrementing the value in the display-start line bits (SL2 to SL0) and display-start raster-row bits (SN3 to SN0) by 1. For example, to smoothly scroll up, first set line bits SN3 to SN0 to 0000, and increment SL2 to SL0 by 1 from 000 to 111 to scroll seven raster-rows. Then increment line bits SN3 to SN0 to 0001, and again increment SL2 to SL0 by 1 from 000 to 111. If the vertical double-height display is at the top of the line, scrolling is done by each two raster-row. When the response speed of the liquid crystal is low or when high-speed scrolling is needed, two- to four-raster-row scrolling is recommended.
60
HD66740
Setting Instructions (10-line Display: NL3-0 = 1001)
Scroll up display
R/W RS DB7 DB6DB5 DB4 DB3 DB2DB1 DB0
0 0
0 0
0 0
1 1
0 0
0 1
1 0
0 0
0 0
0 0
SN3-SN0 = 0000 SL2-SL0 = 000 (1st raster-row of 1st line displayed at the top)
Set 96 x 80-dot initial display data to CGRAM 0 0 01 0 101 00 Scroll up 4 raster-rows (5th raster-row of 1st line displayed at the top)
Update 1st-line (address 000 to 05FH) display data in CGRAM CPU Wait 0 0 0 0 01 01 00 0 10 01 00 100 SN3-SN0 = 0001 SL2-SL0 = 000 (1st raster-row of 2nd line displayed at the top)
Update 1st-line (address 000 to 05FH) display data in CGRAM CPU Wait 0 0 01 0 101 00 Scroll up 12 raster-rows (5th raster-row of 2nd line displayed at the top)
Update 2nd-line (address 100 to 15FH) display data in CGRAM CPU Wait 0 0 0 0 01 01 00 0 10 10 00 100 SN3-SN0 = 0010 SL2-SL0 = 000 (1st raster-row of 3rd line displayed at the top)
Update 2nd-line (address 100 to 15FH) display data in CGRAM CPU Wait 0 0 01 0 101 00 Scroll up 20 raster-rows (5th raster-row of 3rd line displayed at the top)
Update 3rd-line (address 200 to 25FH) display data in CGRAM CPU Wait 0 0 0 0 01 01 00 0 10 11 00 SN3-SN0 = 0011 SL2-SL0 = 000 (1st raster-row of 4th line displayed at the top)
100
Update 3rd-line (address 200 to 25FH) display data in CGRAM CPU Wait 0 0 01 0 101 00 Scroll up 28 raster-rows (5th raster-row of 4th line displayed at the top)
Update 4th-line (address 300 to 35FH) display data in CGRAM CPU Wait
Figure 32
Setting Instructions for Vertical Smooth Scroll
61
HD66740
Partial Smooth Scroll Display Function
The HD66740 can partially fixed-display the areas of a graphics icon, such as a pictogram or a menu bar, and perform vertical smooth scrolling of the remaining bit-map areas. Since the PS1 to PS0 bits do not perform smooth scrolling of the upper first to third display lines but does fixed-display, pictograms can be placed. When CN1 to CN0 bits are set to 10, the first line is displayed at the bottom edge of the LCD screen, and the menu bar can be fixed-displayed at the bottom. This function can largely control the bit-map rewrite frequencies and reduce software loads.
62
HD66740
Table 23
Bit Setting
Bit Setting and Display Lines
CN1-0 = 00 CN1-0 = 10 SN3-0 = 0011
4th line 5th line 6th line 7th line 8th line 9th line 10th line 1st line 2nd line 3rd line
COM Position
SN3-0 = 0000
1st line 2nd line 3rd line 4th line
SN3-0 = 0001
2nd line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line 10th line 1st line
SN3-0 = 0010
3rd line 4th line 5th line 6th line 7th line 8th line 9th line 10th line 1st line 2nd line
SN3-0 = 0011
5th line 6th line 7th line 8th line 9th line 10th line 1st line 2nd line 3rd line 4th line
SN3-0 = 0000
2nd line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line 10th line 1st line
SN3-0 = 0001
3rd line 4th line 5th line 6th line 7th line 8th line 9th line 10th line 1st line 2nd line
SN3-0 = 0010
4th line 5th line 6th line 7th line 8th line 9th line 10th line 1st line 2nd line 3rd line
SN3-0 = 0011
5th line 6th line 7th line 8th line 9th line 10th line 1st line 2nd line 3rd line 4th line
SN3-0 = 0100
6th line 7th line 8th line 9th line 10th line 1st line 2nd line 3rd line 4th line 5th line
COM1
PS1-0 = 00
5th line 6th line 7th line 8th line 9th line 10th line
COM80 COM1
1st line 1st line 2nd line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line
1st line 2nd line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line 10th line
1st line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line 10th line 2nd line
1st line 4th line 5th line 6th line 7th line 8th line 9th line 10th line 2nd line 3rd line
1st line 5th line 6th line 7th line 8th line 9th line 10th line 2nd line 3rd line 4th line
1st line 2nd line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line 1st line
2nd line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line 10th line 1st line
3rd line 4th line 5th line 6th line 7th line 8th line 9th line 10th line 2nd line 1st line
4th line 5th line 6th line 7th line 8th line 9th line 10th line 2nd line 3rd line 1st line
5th line 6th line 7th line 8th line 9th line 10th line 2nd line 3rd line 4th line 1st line
PS1-0 = 01
COM80 COM1
1st line 2nd line 1st line
1st line 2nd line 2nd line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line
1st line 2nd line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line 10th line
1st line 2nd line 4th line 5th line 6th line 7th line 8th line 9th line 10th line 3rd line
1st line 2nd line 5th line 6th line 7th line 8th line 9th line 10th line 3rd line 4th line
2nd line 1st line 2nd line 3rd line 4th line 5th line 6th line 7th line 8th line 1st line
2nd line 2nd line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line 1st line
2nd line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line 10th line 1st line
2nd line 4th line 5th line 6th line 7th line 8th line 9th line 10th line 3rd line 1st line
2nd line 5th line 6th line 7th line 8th line 9th line 10th line 3rd line 4th line 1st line
PS1-0 = 10
2nd line 3rd line 4th line 5th line 6th line 7th line 8th line
COM80 COM1
1st line 2nd line 3rd line 1st line 2nd line 3rd line 4th line 5th line 6th line 7th line
1st line 2nd line 3rd line 2nd line 3rd line 4th line 5th line 6th line 7th line 8th line
1st line 2nd line 3rd line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line
1st line 2nd line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line 10th line
1st line 2nd line 3rd line 5th line 6th line 7th line 8th line 9th line 10th line 4th line
2nd line 3rd line 1st line 2nd line 3rd line 4th line 5th line 6th line 7th line 1st line
2nd line 3rd line 2nd line 3rd line 4th line 5th line 6th line 7th line 8th line 1st line
2nd line 3rd line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line 1st line
2nd line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line 10th line 1st line
2nd line 3rd line 5th line 6th line 7th line 8th line 9th line 10th line 4th line 1st line
PS1-0 = 11
COM80
Notes: 1. The shadow lines above are fixed-displayed. They do not depend on the setting values of the SN3-0 or SL3-0 bits. 2. The SN3-0 and SL3-0 bits specify the next first scroll display line of the fixed-displayed lines. 3. When the drive duty ratio is nine lines (1/72 duty ratio) or less and CN1-0 is 10, the first line shifts to the last displayed line.
63
HD66740
Partial Smooth Scroll Display Examples Table 24 Data Setting to the CGRAM Partial Smooth Scroll Display Examples
CGRAM Address "000" to "06F" "080" to "0EF" "100" to "16F" "180" to "1EF" "200" to "26F" "280" to "2EF" "300" to "36F" "380" to "3EF" "400" to "46F" "480" to "4EF" CGRAM Data
i) Initial screen display - PS1-0 = "10" : Fixed-displays the first and second lines - CN1-0 = "10" : Moves the first line to the bottom edge - SN3-0 = "0010" : Starts display from the third line - SL2-0 = "000"
2nd line (fixed display)
3rd line (Display start position)
Scroll area
1st line (fixed display)
Figure 33
Example of Initial Screen in the Partial Smooth Scroll Mode
64
HD66740
ii) Four-dot partial scroll up - PS1-0 = "10" : Fixed-displays the first and second lines - CN1-0 = "10" : Moves the first line to the bottom edge - SN3-0 = "0010" : Starts display from the third line - SL2-0 = "100" : Shifts up by 4 dots
Fixed display (2nd line)
Display start setting position
Fixed display (1st line)
Figure 34
Example of Display Screen in the Partial Smooth Scroll Mode (1)
iii) 8-dot partial scroll up - PS1-0 = "10" : Fixed-displays the first and second lines - CN1-0 = "10" : Moves the first line to the bottom edge - SN3-0 = "0011" : Starts display from the fourth line - SL2-0 = "000"
Fixed display (2nd line)
Display start setting position
Fixed display (1st line)
Figure 35
Example of Display Screen in the Partial Smooth Scroll Mode (2)
65
HD66740
Double-height Display
The HD66740 can double the height of any desired line from the first to 10th lines. A line can be selected by the DL1 to DL10 bits as listed in table 25. All graphics display patterns stored in the CGRAM can be doubled in height, allowing easy recognition. Note that there should be no space between the lines for double-height display (figure 36). In vertical smooth scrolling, when the display-start setting line is displaying at double height, scrolling can be done by each two-line (dot). Table 25
Bit Setting DL1 = 1 DL2 = 1 DL3 = 1 DL4 = 1 DL5 = 1 DL6 = 1 DL7 = 1 DL8 = 1 DL9 = 1 DL10 = 1
Double-height Display Specifications
Display Position 1st line: double-height 2nd line: double-height 3rd line: double-height 4th line: double-height 5th line: double-height 6th line: double-height 7th line: double-height 8th line: double-height 9th line: double-height 10th line: double-height
- NL3-0 = "1001" (10-line display) - DL2 = 1 - DL8 = 1
Double height display (2nd line)
Double height display (8th line)
Figure 36
Double-height Display (2nd and 8th Lines)
66
HD66740
Reversed Display Function
The HD66740 can display character/graphics display sections by black-and-white reversal. Blackand-white reversal can be easily displayed when REV is set to 1.
REV = 1 (Reversed display)
Figure 37
Reversed Display
67
HD66740
Partial-display-on Function
The HD66740 can program the liquid crystal display drive duty ratio setting (NL3-0 bits), liquid crystal display drive bias value selection (BS2-0 bits), boost output level selection (BT1/0 bit) and contrast adjustment (CT5-0 bits). For example, in the 10-line display mode (1/80 duty ratio), the HD66740 can selectively drive only the center of the screen or only the top or bottom of the screen by combining these register functions and the centering display (CN1-0 bit) function. This is called partial-display-on. Lowering the liquid crystal display drive duty ratio as required saves the liquid crystal display drive voltage, thus reducing internal current consumption. This is suitable for four-line display of a calendar or time, or the display of only graphics icons (pictograms) at the top or bottom of the screen, which needs to be continuous in the system standby state with minimal current consumption. Here, the nondisplayed lines are constantly driven by the unselected level voltage, thus turning off the LCD for the lines. In general, lowering the liquid crystal display drive duty ratio decreases the optimum liquid crystal display drive voltage and liquid crystal display drive bias value. This reduces output multiplying factors in the booster and greatly controls consumption current. Table 26
Item LCD screen
Partial-display-on Function (10-line Display)
Normal 10-line Display 10th line displayed Partial-on Display (Limited 4-line Display) Only four lines on the center of the screen (from the 3rd to 6th lines) Necessary (CN1-0 = 01) 1/32 (NL3-0 = 0011) 1/6 (BS2-0 = 101) 6 V to 8 V (adjustable using CT5-0) Triple (BT1-0 = 00) 88 Hz Only four lines at the top and bottom of the screen (from the 1st to 3rd and 10th lines) Necessary (CN1-0 = 01) 1/32 (NL3-0 = 0011) 1/6 (BS2-0 = 101) 6 V to 8 V (adjustable using CT5-0) Triple (BT1-0 = 00) 88 Hz
LCD drive position shift LCD drive duty ratio LCD drive bias value (optimum) LCD drive voltage*
Not necessary (CN1-0 = 00) 1/80 (NL3-0 = 1001) 1/10 (BS2-0 = 000) 12 V to 15 V (adjustable using CT5-0) Five times (BT1-0 = 10) 70 Hz
Boosting output multiplying factor Frame frequency (fosc = 90 kHz)
Note: The LCD drive voltage depends on the LCD materials which are actually used. Since the LCD drive voltage is high when the LCD drive duty ratio is high, a low duty ratio is suitable for low-power consumption.
68
HD66740
- 1/32 duty drive at the top and bottom of the screen
Always applying non-selection level
Figure 38
Partial-on Display (Date and Time Indicated) (1)
- 1/32 duty drive at the center of the screen
Always applying selection level
Figure 39
Partial-on Display (Date and Time Indicated) (2)
69
HD66740
Sleep Mode
Setting the sleep mode bit (SLP) to 1 puts the HD66740 in the sleep mode, where the device stops all internal display operations, thus reducing current consumption. Specifically, LCD drive is completely halted. Here, all the SEG (SEG1 to SEG112) and COM (COM1 to COM80) pins output the GND level, resulting in no display. If the AMP bit is set to 0 in the sleep mode, the LCD drive power supply can be turned off, reducing the total current consumption of the LCD module. Table 27
Function LCD control R-C oscillation circuit
Comparison of Sleep Mode and Standby Mode
Sleep Mode (SLP = 1) Turned off Operates normally Standby Mode (STB = 1) Turned off Halted
70
HD66740
Standby Mode
Setting the standby mode bit (STB) to 1 puts the HD66740 in the standby mode, where the device stops completely, halting all internal operations including the R-C oscillation circuit, thus further reducing current consumption compared to that in the sleep mode. Specifically, character and segment displays, which are controlled by the multiplexing drive method, are completely halted. Here, all the SEG (SEG1 to SEG112) and COM (COM1 to COM80) pins output the GND level, resulting in no display. If the AMP bit is set to 0 in the standby mode, the LCD drive power supply can be turned off. During the standby mode, no instructions can be accepted other than the start-oscillation. To cancel the standby mode, issue the start-oscillation instruction to stabilize R-C oscillation before setting the STB bit to 0.
Turn off the LCD power supply: AMP = 0 Set standby mode: STB = 1
Standby mode
Issue the start-oscillation instruction Wait at least 10 ms Cancel standby mode: STB = 0 Turn on the LCD drive power supply: AMP = 1
Figure 40
Procedure for Setting and Canceling Standby Mode
71
HD66740
Absolute Maximum Ratings
Item Power supply voltage (1) Power supply voltage (2) Input voltage Operating temperature Storage temperature Symbol VCC VLCD - GND Vt Topr Tstg Unit V V V C C Value -0.3 to +4.6 -0.3 to +16.0 -0.3 to VCC + 0.3 -40 to +85 -55 to +110 Notes* 1, 2 1, 3 1 1, 4 1, 5
Notes: 1. If the LSI is used above these absolute maximum ratings, it may become permanently damaged. Using the LSI within the following electrical characteristics limits is strongly recommended for normal operation. If these electrical characteristic conditions are also exceeded, the LSI will malfunction and cause poor reliability. 2. VCC > GND must be maintained. 3. VLCD > GND must be maintained. 4. For bare die and wafer products, specified up to 85C. 5. This temperature specifications apply to the TCP package.
72
HD66740
DC Characteristics (VCC = 1.8 to 3.6 V, Ta = -40 to +85C*1 )
Item Input high voltage Input low voltage Input low voltage Output high voltage (SDA, DB0-7 pins) Output low voltage (SDA, DB0-7 pins) Output low voltage (SDA, DB0-7 pins) Driver ON resistance (COM pins) Driver ON resistance (SEG pins) I/O leakage current Pull-up MOS current (DB0-7, SDA pins) Symbol Min VIH VIL VIL VOH1 VOL1 V OL1 RCOM RSEG I Li -I p 0.7 VCC -0.3 -0.3 Typ -- -- -- Max VCC Unit Test Condition V VCC = 1.8 to 2.7 V VCC = 2.7 to 3.6 V I OH = -0.1 mA VCC = 1.8 to 2.7 V, I OL = 0.1 mA VCC = 2.7 to 3.6 V, I OL = 0.1 mA Id = 0.05 mA, VLCD = 10 V Id = 0.05 mA, VLCD = 10 V Vin = 0 to VCC VCC = 3 V, Vin = 0 V Notes 2, 3 2, 3 2, 3 2, 4 2 2 5 5 6 2
0.15 VCC V 0.15 VCC V -- 0.2 VCC V V
0.75 VCC -- -- -- -- -- -1 1 -- -- -- 3 3 -- 10 32
0.15 VCC V 20 30 1 40 55 k k A A A
Current consumption I OP during normal operation (VCC-GND) Current consumption during sleep mode (VCC-GND) Current consumption during standby mode (VCC-GND) I SL
R-C oscillation, 7, 8 VCC = 3 V, Ta = 25 C, f OSC = 86 kHz (1/72 duty) R-C oscillation, 7, 8 VCC = 3 V, Ta = 25 C, f OSC = 86 kHz (1/72 duty) VCC = 3 V, Ta = 25C 7, 8
--
11
--
A
I ST
--
0.1
5
A
LCD drive power supply I LCD current (VLCD-GND) LCD drive voltage (VLCD - GND) VLCD
--
20
35
A
VLCD = 12 V, 8 Ta = 25 C, f OSC = 86 kHz, 1/9 bias, VTEST3="High" 9
4.5
--
15.0
V
Note: For the numbered notes, refer to the Electrical Characteristics Notes section following these tables.
73
HD66740
Booster Characteristics
Item Triple-boost output voltage (VLOUT pin) Quadrupleboost output voltage (VLOUT pin) Five-timesboost output voltage (VLOUT pin) Use range of boost output voltage Symbol V UP3 Min 8.5 Typ 8.9 Max 9.0 Unit V Test Condition VCC = Vci = 3.0 V, I O = 30 A, C = 1 F, f OSC = 86 kHz, Ta = 25C VCC = Vci = 3.0 V, I O = 30 A, C = 1 F, f OSC = 86 kHz, Ta = 25C VCC = Vci = 3.0 V, I O = 30 A, C = 1 F, f OSC = 86 kHz, Ta = 25C For triple to Five-times boost Notes 12
V UP4
11.5
11.8
12.0
V
12
V UP5
14.5
14.8
15.0
V
12
VUP3 , VUP4 , VUP5
VCC
--
15.0
V
12
Note: For the numbered notes, refer to the Electrical Characteristics Notes section following these tables.
74
HD66740
AC Characteristics (VCC = 1.8 to 3.6 V, Ta = -40 to +85C*1 )
Clock Characteristics (V CC = 1.8 to 3.6 V)
Item External clock frequency External clock duty ratio External clock rise time External clock fall time R-C oscillation clock Symbol fcp Duty trcp tfcp f OSC Min 50 45 -- -- 69 Typ 75 50 -- -- 86 Max 100 55 0.2 0.2 103 Unit kHz % s s kHz Rf = 270 k, VCC = 3 V Test Condition Notes 10 10 10 10 11
Note: For the numbered notes, refer to the Electrical Characteristics Notes section following these tables.
68-system Bus Interface Timing Characteristics (Vcc = 1.8 to 2.7 V)
Item Enable cycle time Write Read Enable high-level pulse width Write Read Enable low-level pulse width Write Read Enable rise/fall time Setup time (RS, R/W to E, CS*) Address hold time Write data setup time Write data hold time Read data delay time Read data hold time Symbol t CYCE t CYCE PWEH PWEH PWEL PWEL t Er, t Ef t ASE t AHE t DSWE t HE t DDRE t DHRE Min 600 800 120 350 300 300 -- 50 20 60 20 -- 5 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- 25 -- -- -- -- 300 -- ns ns ns ns ns ns ns Figure 47 Figure 47 Figure 47 Figure 47 Figure 47 Figure 47 Figure 47 ns Figure 47 ns Figure 47 Unit ns Test Condition Figure 47
75
HD66740
(Vcc = 2.7 to 3.6 V)
Item Enable cycle time Write Read Enable high-level pulse width Write Read Enable low-level pulse width Write Read Enable rise/fall time Setup time (RS, R/W to E, CS*) Address hold time Write data setup time Write data hold time Read data delay time Read data hold time Symbol t CYCE t CYCE PWEH PWEH PWEL PWEL t Er, t Ef t ASE t AHE t DSWE t HE t DDRE t DHRE Min 380 500 70 250 150 150 -- 50 20 60 20 -- 5 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- 25 -- -- -- -- 200 -- ns ns ns ns ns ns ns Figure 47 Figure 47 Figure 47 Figure 47 Figure 47 Figure 47 Figure 47 ns Figure 47 ns Figure 47 Unit ns Test Condition Figure 47
76
HD66740
80-system Bus Interface Timing Characteristics (Vcc = 1.8 to 2.7 V)
Item Bus cycle time Write Read Write low-level pulse width Read low-level pulse width Write high-level pulse width Read high-level pulse width Write/Read rise/fall time Setup time (RS to CS*, WR*, RD*) Address hold time Write data setup time Write data hold time Read data delay time Read data hold time Symbol t CYCW t CYCR PWLW PWLR PWHW PWHR t WRr , WRf t AS t AH t DSW tH t DDR t DHR Min 600 800 120 350 300 300 -- 50 20 60 20 -- 5 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- 25 -- -- -- -- 300 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Test Condition Figure 48 Figure 48 Figure 48 Figure 48 Figure 48 Figure 48 Figure 48 Figure 48 Figure 48 Figure 48 Figure 48 Figure 48 Figure 48
(Vcc = 2.7 to 3.6 V)
Item Bus cycle time Write Read Write low-level pulse width Read low-level pulse width Write high-level pulse width Read high-level pulse width Write/Read rise/fall time Setup time (RS to CS*, WR*, RD*) Address hold time Write data setup time Write data hold time Read data delay time Read data hold time Symbol t CYCW t CYCR PWLW PWLR PWHW PWHR t WRr, WRf t AS t AH t DSW tH t DDR t DHR Min 380 500 70 250 150 150 -- 50 20 60 20 -- 5 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- 25 -- -- -- -- 200 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Test Condition Figure 48 Figure 48 Figure 48 Figure 48 Figure 48 Figure 48 Figure 48 Figure 48 Figure 48 Figure 48 Figure 48 Figure 48 Figure 48
77
HD66740
Clock-synchronized Serial Interface Timing Characteristics (V CC = 1.8 to 3.6 V) (V CC = 1.8 to 2.55 V)
Item Serial clock cycle time At write (receive) At read (send) Serial clock high-level width At write (receive) At read (send) Serial clock low-level width At write (receive) At read (send) Serial clock rise/fall time Chip select setup time Chip select hold time Serial input data setup time Serial input data hold time Serial output data delay time Serial output data hold time Symbol t SCYC t SCYC t SCH t SCH t SCL t SCL t scf, t scr t CSU t CH t SISU t SIH t SOD t SOH Min 0.5 1 230 480 230 480 -- 60 200 100 100 -- 5 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max 20 20 -- -- -- -- 20 -- -- -- -- 400 -- Unit s s ns ns ns ns ns ns ns ns ns ns ns Test Condition Figure 49 Figure 49 Figure 49 Figure 49 Figure 49 Figure 49 Figure 49 Figure 49 Figure 49 Figure 49 Figure 49 Figure 49 Figure 49
78
HD66740
(V CC = 2.55 to 3.6 V)
Item Serial clock cycle time At write (receive) At read (send) Serial clock high-level width At write (receive) At read (send) Serial clock low-level width At write (receive) At read (send) Serial clock rise/fall time Chip select setup time Chip select hold time Serial input data setup time Serial input data hold time Serial output data delay time Serial output data hold time Symbol t SCYC t SCYC t SCH t SCH t SCL t SCL t scf, t scr t CSU t CH t SISU t SIH t SOD t SOH Min 0.2 0.5 80 230 80 230 -- 60 200 40 40 -- 5 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max 20 20 -- -- -- -- 20 -- -- -- -- 200 -- Unit s s ns ns ns ns ns ns ns ns ns ns ns Test Condition Figure 49 Figure 49 Figure 49 Figure 49 Figure 49 Figure 49 Figure 49 Figure 49 Figure 49 Figure 49 Figure 49 Figure 49 Figure 49
Reset Timing Characteristics (V CC = 1.8 to 3.6 V)
Item Reset low-level width Symbol t RES Min 1 Typ -- Max -- Unit ms Test Condition Figure 50
79
HD66740
I2C Bus Interface Timing Characteristics (Vcc = 1.8 to 3.6 V)
Item SCL clock frequency SCL clock SCL clock high-level pulse width low-level pulse width Symbol Min f SCL t SCLH t SCLL t Sr t Sf t BUF t STAH t STAS t STOS t SDAS t SDAH t SP 0 120 240 10 10 240 320 320 320 40 0 0 Typ -- -- -- -- -- -- -- -- -- -- -- -- Max 1300 -- -- 160 70 -- -- -- -- -- -- 10 Unit kHz ns ns ns ns ns ns ns ns ns ns ns Test Condition Figure 51 Figure 51 Figure 51 Figure 51 Figure 51 Figure 51 Figure 51 Figure 51 Figure 51 Figure 51 Figure 51 Figure 51
SCL/SDA rise time SCL/SDA fall time Bus free time Start condition hold time Setup time for a repeated START condition Setup time for STOP condition SDA data setup time SDA data hold time SCL/SDA spike pulse width
80
HD66740
Electrical Characteristics Notes
1. For bare die products, specified up to 85C. 2. The following three circuits are I/O pin configurations (figure 41).
Pins: RESET*, CS*, E/WR*/SCL, RS, OSC1, OPOFF, IM2/1, IM0/ID, TEST Vcc PMOS NMOS Vcc PMOS NMOS Pin: OSC2
GND Pin: RW/RD*/SDA
GND
Vcc Vcc
(Pull-up MOS) PMOS
PMOS (Input circuit) NMOS Vcc PMOS (Tri-state output circuit) Output enable Output data IM1 NMOS
GND IM2
Pin: DB7 to DB0 Vcc PMOS (Input circuit) NMOS Vcc PMOS (Tri-state output circuit) Output enable Output data IM1 NMOS
GND
Figure 41
I/O Pin Configuration
81
HD66740
3. The TEST pin must be grounded and the IM2/1, IM0/ID, and OPOFF pins must be grounded or connected to Vcc. 4. Corresponds to the high output for clock-synchronized serial interface. 5. Applies to the resistor value (RCOM) between power supply pins V1OUT, V2OUT, V5OUT, GND and common signal pins, and resistor value (RSEG) between power supply pins V1OUT, V3OUT, V4OUT, GND and segment signal pins, when current Id is flown through all driver output pins. 6. This excludes the current flowing through pull-up MOSs and output drive MOSs. 7. This excludes the current flowing through the input/output units. The input level must be fixed high or low because through current increases if the CMOS input is left floating. 8. The following shows the relationship between the operation frequency (fosc) and current consumption (Icc) (figure 42).
Vcc = 3 V
Vcc = 3 V, fosc = 86 kHz
60
Display on (typ.)
30
typ.
40
Iop (A)
20
Sleep (typ.)
ILCD (A)
20
Standby (typ.)
10 0
0
0
20 40 60 80 100
R-C oscillation frequencies: fosc (kHz)
8.0
10.0
12.0
14.0
LCD drive voltage: VLCD (V)
Figure 42
Relationship between the Operation Frequency and Current Consumption
9. Each COM and SEG output voltage is within 0.15 V of the LCD voltage (Vcc, V1, V2, V3, V4, V5) when there is no load. 10. Applies to the external clock input (figure 43).
1.5k to 2k Oscillator Open OSC1 OSC2 0.7Vcc 0.5Vcc 0.3Vcc t rcp t fcp Duty = Th Tl Th Th+Tl
x100
Figure 43
External Clock Supply
82
HD66740
11. Applies to the internal oscillator operations using external oscillation resistor Rf (figure 44 and table 28).
OSC1 Rf OSC2
Since the oscillation frequency varies depending on the OSC1 and OSC2 pin capacitance, the wiring length to these pins should be minimized.
Figure 44 Table 28
Internal Oscillation
External Resistance Value and R-C Oscillation Frequency (Referential Data)
External Resistance (Rf) 200 k 270 k 300 k 330 k 360 k 390 k 430 k 470 k R-C Oscillation Frequency: fosc Vcc = 1.8 V 89 kHz 70 kHz 65 kHz 60 kHz 55 kHz 52 kHz 48 kHz 44 kHz Vcc = 2.2 V 103kHz 80 kHz 73 kHz 68 kHz 62 kHz 58 kHz 53 kHz 48 kHz Vcc = 3.0 V 115 kHz 88 kHz 80 kHz 74 kHz 68 kHz 64 kHz 58 kHz 52 kHz Vcc = 3.6 V 121 kHz 92 kHz 83 kHz 77 kHz 71 kHz 66 kHz 60 kHz 54 kHz
12. Booster characteristics test circuits are shown in figure 45.
(Quadruple boosting) (Five-times boosting)
Vcc
Vci C1+ C1C2+ C2C3+ C3C4+ C4-
+ + +
Vcc 1 F 1 F 1 F
Vci C1+ C1C2+ C2C3+ C3C4+ C4-
+ + + +
1 F 1 F 1 F 1 F
GND
VLOUT VLCD
+
1 F
GND
VLOUT VLCD
+
1 F
Figure 45
Booster
83
HD66740
Referential data VUP4 = VLCD - GND; VUP5 = VLCD - GND (i) Relation between the obtained voltage and input voltage Quadruple boosting typ. 16.0 15.0 VUP4 (V) 12.0 8.0 4.0 1.0 2.0 3.0 Vci (V) 4.0 VUP5 10.0 5.0 1.0 2.0 3.0 Vci (V) 4.0 typ. Five-times boosting
Vci = Vcc, fosc = 86 kHz, Ta = 25C DCC = 0 (ii) Relation between the obtained voltage and temperature Quadruple boosting 14.0 typ. 12.0 VUP4 (V) 10.0 8.0 VUP5 16.0 14.0 12.0
Vci = Vcc, fosc = 86 kHz, Ta = 25C DCC = 0
Five-times boosting
typ.
-60
-20 0 20 Ta (C)
60
100
-60
-20 0 20 60 Ta (C)
100
Vci = Vcc = 3 V, fosc = 86 kHz, Io = 30A DCC = 0 (iii) Relation between the obtained voltage and capacity Quadruple boosting 13.0 typ. 12.0 VUP4 (V) 11.0 10.0 9.0 VUP5 (V)
Vci = Vcc = 3 V, fosc = 86 kHz, Io = 30A DCC = 0
Five-times boosting 16.0 typ. 15.0 14.0 13.0
0.5
1.0 C (F)
1.5
12.0
0.5
1.0 C (F)
1.5
Vci = Vcc = 3.0 V, fosc = 86 kHz, Io = 30 A DCC = 0
Vci = Vcc = 3.0 V, fosc = 86 kHz, Io = 30 A DCC = 0
Figure 45
Booster (cont)
84
HD66740
(iv) Relation between the obtained voltage and current Quadruple boosting Five-times boosting
12.5 12.0
VUP4 (V) 11.5 10.0
typ.
15.5 15.0 VUP5 (V) 14.5 14.0 13.5
typ.
9.5 0 50 100 Io (A) 150 200
0
50
100 150 Io (A)
200
Vci = Vcc = 3.0 V, fosc = 86 kHz, Ta = 25 C DCC = 0
Vci = Vcc = 3.0 V, fosc = 86 kHz, Ta = 25 C DCC = 0
Figure 45
Booster (cont)
Load Circuits
AC Characteristics Test Load Circuits
Data bus: DB7 to DB0, SDA Test Point
50 pF
Figure 46
Load Circuit
85
HD66740
Timing Characteristics
68-system Bus Operation
RS R/W
V IH V IL
VIH VIL
tASE
tAHE
VIL
CS*
V IL
PWEH
*1
PW EL
V IH
V IL
E
V IH
VIL
VIL
tEr
tEf tDSWE tCYCE tHE
VIH V IL
DB0 to DB7
tDDRE
VIH V IL
Write data
tDHRE
VOH1 VOL1
DB0 to DB7
Read data
V OH1 V OL1
Note 1: PWEH is specified in the overlapped period when CS* is low or E is high.
Figure 47
68-system Bus Timing
86
HD66740
80-system Bus Operation
RS
V IH V IL
V IH V IL
tAS
tAH
VIH
CS*
VIL
PW LW, PW LR
*1
PWHW PWHR
WR* RD*
VIH V IL
VIH V IL
VIH
tWRr tCYCW, tCYCR tDSW
tWRf tHWR
VIH V IL
DB0 to DB7
tDDR
V IH V IL
Write data tDHR
DB0 to DB7
V OH1 V OL1
Read data
V OH1 V OL1
Note 1: PW LW and PW LR are specified in the overlapped period when CS* is low or WR* or RD* is low.
Figure 48
80-system Bus Timing
87
HD66740
Clock-synchronized Serial Operation
Start: S
End: P
CS*
VIL
VIL
tCSU SCL
VIH VIL
tscr
tSCYC tscf tCWL tSCH
VIH VIH VIL VIL
tCH
VIH
VIL
tSISU SDA
VIH VIL
tSIH
VIH
Input data
VIL
Input data tSOH
tSOD SDA
Figure 49 Reset Operation
VOH1 VOH1
Output data
VOH1 Output data VOL1
Clock-synchronized Serial Interface Timing
tRES
RESET*
VIL
VIL
Figure 50
Reset Timing
88
HD66740
I2C Bus Operation
Stop : P Start : S Re peat ed Start : Sr S top : P
VIH
SD A
VIH VIL2
VIH VIL2
VIH
VIH VIL2
VIL2
tS DAH tBU F tSTAH
SCL
VIH VIL2 VIH
tSDAS tSP tSTAS
VIH
tSCL tSCLH
tSTOS
tSf
tSCLL
tSr
Figure 51
I2C bus Interface Timing
89
HD66740
Power-on/off Sequence
To prevent pulse lighting of LCD screens at power-on/off, the power-on/off sequence is activated as shown below. However, since the sequence depends on LCD materials to be used, confirm the conditions by using your own system. Power-on Sequence
Turn on power voltages Vcc and Vci, RESET = "Low"
Wait for 1 ms or longer (power-on time)
Wait for 10 ms or longer (oscillation stabilization time)
Issue LCD power instruction
Issue use-state instruction
Wait for 10-150 ms or longer (op-amplifier output stabilization time)
Note: Depends on the external capacitance of V1OUT to V5OUT.
Turned on display: D = 1
Figure 52
Power-on Sequence
90
HD66740
Vcc Power voltage: Vcc GND Power-on reset time: 1 ms
Vcc RESET GND
Oscillation state
Oscillation stabilization time: 10 ms Vcc Signal-input instruction issued GND
Note: CR oscillation starts by power-on and input reset. The standby mode is cleared by input reset.
Figure 53
Power-on Timing
91
HD66740
Power-off Sequence
Turn off display: D = 0
Issue LCD power instruction
Turn off power voltages Vcc and Vci
To the power-on sequence
Figure 54
Power-off Sequence
Vcc Power voltage: Vcc GND
Power is turned off.
Vcc RESET GND V1OUT Driver SEG/ COM output GND
RESET is input as soon as possible.
Note: When hardware reset is input during the power-off period, the D bit is cleared to 0 and SEG/COM output is forcibly lowered to the GND level.
Figure 55
Power-off Timing
92
HD66740
Modification history
Revision 0.1 (Feb. 15. 2000) First release
Revision 0.2 (5. May. 2000) Change pad pitch from 60um to 50um. Added LCD-Driving-Pattern Control instruction
Revision 0.3 (1. July. 2000) Added pad arrangement figure and coordinate table Change figure 41 (remove pull-up MOS from DB7 to DB0)
Revision 0.4 (September. 2000) Added RS pin explanation when serial interface mode is used. Added standard TCP (TB0) drawing.
Revision 0.5 (November. 2000) Remove cursor display related explanations. Remove character and super-imposed display related explanations.
Revision 0.6 (January. 2001) Support 1.8V low voltage operation. Corrected corner PAD number (p6). Added VTEST usage (p48) and operational amplifier usage (p49). Changed R-C Oscillation Frequency of Table 28 (p83). Added I2C interface (HCD66740WBP, HD66740WTB0).
Revision 0.7 (January. 2001) Added power on/off sequence.
HD66740
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